Methods and systems for adjusting phase lock loop devices

A system comprising:

• a sampler configured to generate samples using a first data stream;
• a clock and data recovery (CDR) circuit configured to determine a phase offset using at least the samples and generate a first control code;
• a first phase interpolator configured to generate a first clock signal using at least the first control code and a second clock signal;
• a first filter configured to generate a second control code by determining a movement of the first phase interpolator using at least the first control code;
• a reference clock configured to provide a third clock signal;
• and
• a phase-lock loop circuit configured to generate the second clock signal using the third clock signal and the second control code.

A system comprising:

• a sampler configured to generate samples using a first data stream and a first clock signal;
• a clock and data recovery (CDR) circuit configured to generate a first control code using at least the samples;
• a first phase interpolator configured to generate the first clock signal using at least the first control code and a second clock signal;
• a first filter configured to generate a second control code by determining a movement of the first phase interpolator using at least the first control code;
• a reference clock configured to provide a third clock signal;
• and
• a first phase-lock loop circuit configure to generate the second clock signal using the third clock signal and the second control code.