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US 9,036,764 B1Granted
Clock recovery circuit
AssigneeRambus Inc.
InventorsMasum Hossain, Jared L. Zerbe, Myeong-Jae Park
Life of this patent
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AssigneeRambus Inc.
InventorsMasum Hossain, Jared L. Zerbe, Myeong-Jae Park
Estimating the term…
This disclosure provides a clock recovery circuit having a phase-locked loop (PLL) with two-point modulation. A binary phase-error signal controls a variable frequency oscillator's (VFO's) feedback path, while a linear phase-error signal controls the PLL outside of that feedback path. The linear phase-error signal is injected using an ultra-low latency delay path. While the binary phase-error signal sets the lock-point of the PLL, the linear phase-error path dominates at high frequencies and also helps reduce dither jitter. Other optional features include an area-efficient hybrid phase detector that generates both the binary and linear phase-error signals, use of a phase interpolator inside the PLL to further smooth dither jitter, recovered clock update filtering for specific data transitions, and support for multi-PAM signaling.
A clock recovery circuit, comprising:
An improvement in a clock recovery circuit having a phase-locked loop, circuitry operable to determine whether transitions of a recovered clock are early or late relative to an incoming data signal and to responsively generate a binary phase-error signal, a variable frequency oscillator operable to generate the recovered clock, and circuitry operable to generate in response to the binary phase-error signal a control signal having a magnitude, the frequency of the variable frequency oscillator dependent on the magnitude of the control signal, the improvement comprising:
A clock recovery circuit operable to receive an input data signal, the clock recovery circuit comprising:
Dependencies are inferred from the claim text.