US 12,756,535 B2 · Asynchronous sampling rate converter

Abstract

Aspects of the disclosure relate to asynchronous sampling rate conversion of digital data. A sampling rate conversion module may use, for sampling rate conversion, a bank of subfilters corresponding to a polyphase interpolator. The specific subfilters and/or filter coefficients to be used for generation of output samples may be based on a rate control value. The rate control value may be determined based on a sampling rate used for input samples of the sampling rate converter and a read-out rate associated with samples, generated by the sampling rate converter, stored in an output buffer. A phase-locked loop (PLL) or other control loop may be used to maintain the rate control value at an appropriate level to negate the effects of temperature variations, noise, or any other system variations on the sampling rates.

Claims20

Dependent claims

A method comprising:

determining, by a computing device and based on packet time stamps associated with input data packets of a signal, a packet write rate;
determining, based on a local clock of the computing device, a packet read rate associated with output data packets;
determining, based on a ratio of the packet write rate and the packet read rate, a rate control value;
and
generating, based on the rate control value, a first quantity of output samples in one or more output data packets based on a second quantity of input samples in one or more input data packets, wherein a rate of generation of the first quantity of output samples corresponds to the packet read rate.

2 more elements

Dependencies are inferred from the claim text.

Asynchronous sampling rate converter

Life of this patent

Asynchronous sampling rate converter

Life of this patent

Abstract

Claims20