G11C 7/1027
Static column decode serial bit line access mode, i.e. using an enabled
Official title: {Static column decode serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled bit line addresses}
G11C7/1027 (Static column decode serial bit line access mode, i.e. using an enabled) appears on 195 US grants and 173 published applications in this corpus.
Search patents in G11C- Granted patents
- 195
- Published applications
- 173
- Assignees
- 69
- Inventors
- 278
- Latest grant
- 19 Aug 2025
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1988 | 1 | 0 |
| 1989 | 1 | 0 |
| 1990 | 0 | 0 |
| 1991 | 0 | 0 |
| 1992 | 0 | 0 |
| 1993 | 1 | 0 |
| 1994 | 0 | 0 |
| 1995 | 2 | 0 |
| 1996 | 2 | 0 |
| 1997 | 2 | 0 |
| 1998 | 3 | 0 |
| 1999 | 7 | 0 |
| 2000 | 4 | 0 |
| 2001 | 4 | 3 |
| 2002 | 3 | 9 |
| 2003 | 9 | 13 |
| 2004 | 13 | 17 |
| 2005 | 6 | 13 |
| 2006 | 24 | 22 |
| 2007 | 15 | 23 |
| 2008 | 15 | 14 |
| 2009 | 15 | 14 |
| 2010 | 13 | 15 |
| 2011 | 16 | 3 |
| 2012 | 9 | 6 |
| 2013 | 0 | 3 |
| 2014 | 6 | 3 |
| 2015 | 5 | 1 |
| 2016 | 3 | 1 |
| 2017 | 2 | 1 |
| 2018 | 2 | 2 |
| 2019 | 2 | 1 |
| 2020 | 2 | 1 |
| 2021 | 2 | 2 |
| 2022 | 1 | 0 |
| 2023 | 2 | 4 |
| 2024 | 2 | 0 |
| 2025 | 1 | 2 |
By publication year. Applications have been published since 2001.
Recent patents
- Lean command sequence for multi-plane read operations19 Aug 2025US 12,393,367 B2Intel NDTM US LLC
- SRAM design for energy efficient sequential access20 Aug 2024US 12,068,054 B2Meta Platforms Technologies, LLC
- Computer device, setting method for memory module and mainboard16 Jan 2024US 11,875,872 B2Giga-Byte Technology Co., Ltd.
- Transition structures for three-dimensional memory arrays12 Sep 2023US 11,756,596 B1Micron Technology, Inc.
- System and method for reading and writing memory management data through a non-volatile cell based register8 Aug 2023US 11,721,372 B2Micron Technology, Inc.
- Lean command sequence for multi-plane read operations18 Dec 2025US 2025/0383821 A1Intel NDTM US LLC
- Pulse signal generator to reduce power consumption of sram and sram having the same12 Jun 2025US 2025/0191651 A1UIF (University Industry Foundation), Yonsei University
- Computer device, setting method for memory module and mainboard6 Jul 2023US 2023/0215475 A1Giga-Byte Technology Co., Ltd.
- Sram design for energy efficient sequential access9 Mar 2023US 2023/0075959 A1Meta Platforms Technologies, LLC
- Lean command sequence for multi-plane read operations2 Mar 2023US 2023/0062668 A1Intel Corporation
Most cited
By later US patents
- Synchronous memory device with dual page and burst mode operations275US 5,966,724 AMicron Technology, Inc. · 1999
- Flash memory circuit and method of operation146US 5,263,003 AAllen-Bradley Company, Inc. · 1993
- Method for switching between modes of operation141US 6,615,325 B2Micron Technology, Inc. · 2003
- Synchronous DRAM memory with asynchronous column decode136US 5,666,321 AMicron Technology, Inc. · 1997
- Memory circuit81US 6,172,936 B2Fujitsu Limited · 2001