Back to results
US 6,172,936 B2Granted
Memory circuit
AssigneeFujitsu Limited
InventorKazuhiro Kitazaki
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeFujitsu Limited
InventorKazuhiro Kitazaki
Estimating the term…
The present invention comprises a flash memory or similar nonvolatile memory circuit characterized by a constitution that enables read operations in two modes, a clock-synchronous burst read mode and a clock-asynchronous normal read mode, the device being set to normal read mode in response to power on, and being set to burst read mode in response to a control signal instructing the burst read mode. The memory device includes a burst mode switching circuit internally. This burst mode switching circuit sets an output circuit to normal read mode in response to the power ON so as to enable read operations not synchronized with the clock after the power ON. In response to a burst mode control signal provided by the system, the burst mode switching circuit sets the output circuit to burst read mode. Thus, the system can perform the burst read to the nonvolatile memory device under the environment analogous to conventional main memory access.
A memory circuit including nonvolatile memory cells, comprising:
A memory circuit switchable in response to a burst control signal between a clock-synchronous first read mode and a clock-asynchronous second read mode:
Dependencies are inferred from the claim text.