Synchronous DRAM memory with asynchronous column decode

A control circuit for an array of memory cells which are arranged in rows and columns and which are in communication with a microprocessor through the use of a memory control module that provides control signals to the control circuit and that sends a row-address and a column-address of a selected memory cell to be communicated with by the microprocessor to the control circuit, the control circuit comprising:

• (a) means for decoding the column-address;
• (b) an address bus communicating between the memory control module and the means for decoding the column-address, the address bus alternately being provided by the memory control module with the column-address and the row-address;
• (c) internal logic means for responding to the memory control module in order to generate an internal command that enable the array of memory cells to produce and receive data;
• (d) synchronizing means for coordinating a row-address decoding operation, the beginning of which is dictated by the internal command from the internal logic means, such that the row-address decoding operation begins only between predetermined repeating intervals;
• and
• (e) means for sensing the occurrence of a new column-address on the address bus in order that the means for decoding the column-address, independently of the predetermined repeating intervals of the synchronizing means, may begin decoding a new column-address as soon as the new column-address appears on the address bus.

A control circuit for an array of memory cells which are arranged in rows and columns and which are in communication with a microprocessor through the use of a memory control module that provides control signals to the control circuit and that sends a row-address and a column-address of a selected memory cell to be communicated with by the microprocessor to the control circuit, the control circuit comprising:

• (a) a decoder circuit receiving address data from an address bus communicating between the memory control module and the decoder circuit and decoding the address data to provide an address to the array of memory cells;
• (b) an internal logic control circuit in communication with the memory control module for generating internal control signals;
• (c) a clock signal to which at least a substantial portion of said internal control signals by the internal logic control circuitry are synchronized;
• (d) a column-address latch between the address bus and the decoder circuit;
• (e) a communication line between the internal logic control circuit and a decode latch that provides a control signal to the decode latch for making the decode latch transparent;
• (f) an address transition detection circuit for detecting when a new column-address is present on the address bus and for enabling the column-address latch to receive the new column-address, such that the decoder circuit can begin decoding the new column-address independently of the clock signal;
• (g) a post-decode latch located between the decoder circuit and the array of memory cells, the post-decode latch prohibiting a decoded column-address from transferring from the decoder circuit until the decoder circuit is enabled;
• and
• (h) a communication line extending between the internal logic control circuit and the post-decode latch for enabling the post-decode latch when the memory control module has verified that the new column-address is present on the address bus.

A method of addressing a memory cell array, the method comprising:

• (a) providing address bus lines;
• (b) providing a memory circuit including a memory array;
• (c) providing an external logic control for placing a separate column and row-address in the address bus lines and for generating a RAS signal when the row-address is stable and a CAS signal when the column-address is stable;
• (d) providing a synchronizing clock signal for synchronizing at least a significant portion of all operations conducted in response to the external logic control;
• (e) providing a row-address decoding circuit for decoding the row-address in response to the RAS signal;
• (f) providing a column-address decoding circuitry and a column-address latch previous to the column-address decoding circuitry for separating the column-address decoding circuitry from the address bus lines, the column-address latch being set to a transparent state in response to the reception of the RAS signal;
• (g) providing an address transition detection circuit for detecting when a new column-address appears on the address bus line, wherein the address transition detection circuit is in communication with the column-address latch for enabling the column-address latch when a new column-address is present on the bus lines;
• (h) providing the row-address on the address bus lines and providing the RAS signal to notify that the column-address is stable;
• (i) decoding the row-address;
• (j) providing a column-address on the address bus lines;
• (k) sensing the presence of the column-address on the address bus lines with the address transition detection circuit and passing the column-address to the column-address decoding circuitry;
• (l) decoding the column-address with the column-address decoding circuitry;
• (m) providing a CAS signal to the column-address decoding circuitry that the column-address is the desired column-address and is stable and should be passed into the memory array;
• (n) latching the column-address and allowing no new column-address to be decoded by the column-address decoding circuitry until the occurrence of a subsequent RAS signal;
• and
• (o) conducting a data communication operation by the memory cell array.