Lean command sequence for multi-plane read operations
AssigneeIntel NDTM US LLC
InventorsNaveen Vittal Prabhu, Aliasgar Madraswala, Sandeep Rasoori, Trupti Bemalkhedkar
Life of this patent
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Abstract
Systems, apparatuses and methods may provide for technology that generates address information for a plurality of planes in NAND memory, excludes column information from the address information, and sends a read command sequence to the NAND memory, wherein the read command sequence includes the address information. In one example, the technology also excludes plane confirm commands and busy cycles from the read command sequence.
Claims16
A semiconductor apparatus comprising:
- one or more substrates;
- and
- logic coupled the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic to:
- generate address information for a plurality of planes in NAND memory;
- exclude column addresses from the address information;
- send a read command sequence to the NAND memory, wherein the read command sequence includes the address information;
- and
- exclude plane confirm commands and busy cycles from the read command sequence.
A memory device comprising:
- a NAND memory;
- and
- a controller coupled to the NAND memory, wherein the controller includes logic coupled to one or more substrates, the logic to:
- generate address information for a plurality of planes in the NAND memory,
- exclude column addresses from the address information,
- send a read command sequence to the NAND memory, wherein the read command sequence includes the address information, and
- exclude plane confirm commands and busy cycles from the read command sequence.
At least one computer readable storage medium comprising a set of instructions, which when executed by a controller, cause the controller to:
- generate address information for a plurality of planes in NAND memory;
- exclude column addresses from the address information;
- send a read command sequence to the NAND memory, wherein the read command sequence includes the address information;
- and
- exclude plane confirm commands and busy cycles from the read command sequence.
A method comprising:
- generating address information for a plurality of planes in NAND memory;
- excluding column addresses from the address information;
- sending a read command sequence to the NAND memory, wherein the read command sequence includes the address information;
- and
- excluding plane confirm commands and busy cycles from the read command sequence.
Dependencies are inferred from the claim text.