US 11,756,596 B1Granted

Transition structures for three-dimensional memory arrays

AssigneeMicron Technology, Inc.

InventorsShuangqiang Luo, Indra V. Chary, Lifang Xu

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Abstract

Methods, systems, and devices for transition structures for three-dimensional memory arrays are described. A memory device may include a staircase region which includes a set of vias. The set of vias may include a first subset of vias which couple respective word line plates of the memory region with associated word line decoders, and a second subset of vias which are electrically isolated from the word line plates. The second subset of vias may be arranged in one or more rows positioned between the first subset of vias and the memory region. In some cases, the second subset of vias may be positioned above respective conductive contacts. Additionally or alternatively, the second subset of vias may be positioned above a common conductor shared with pillars of the memory region.

Claims25

Dependent claims

An apparatus, comprising:

a plurality of access line decoders at least partially in a substrate;
a plurality of word line plates arranged vertically above the substrate and separated from each other by respective dielectric layers, each word line plate comprising a plurality of word line members that each extend in a first horizontal direction and into a memory region;
a first plurality of vias extending vertically through the plurality of word line plates, the first plurality of vias arranged in rows extending in the first horizontal direction and columns extending in a second horizontal direction, each via of the first plurality of vias coupled with a respective access line decoder of the plurality of access line decoders;
and
a second plurality of vias extending vertically through the plurality of word line plates, each via of the second plurality of vias electrically isolated from the plurality of access line decoders, and a subset of the second plurality of vias arranged in a column extending in the second horizontal direction and in between the first plurality of vias and the memory region in the first horizontal direction.

2 more elements

A method, comprising:

depositing a stack of layers vertically over a substrate, the stack of layers comprising alternating layers of a first material and a second material, the first material comprising a dielectric material, and the substrate comprising a plurality of access line decoders;
etching a plurality of cavities through the stack of layers, the plurality of cavities arranged in rows extending in a first horizontal direction and columns extending in a second horizontal direction;
and
depositing a conductive material in the plurality of cavities to form a first plurality of vias in a first subset of the plurality of cavities and a second plurality of vias in a second subset of the plurality of cavities, each of the first plurality of vias coupled with a respective access line decoder of the plurality of access line decoders, and each of the second plurality of vias electrically isolated from the plurality of access line decoders, and each of the second plurality of vias located between the first plurality of vias and a memory region in the first horizontal direction, the memory region comprising memory cells formed in the stack of layers.

1 more element

A memory array formed by a process comprising:

depositing a stack of layers vertically over a substrate, the stack of layers comprising alternating layers of a first material and a second material, the first material comprising a dielectric material, and the substrate comprising a plurality of access line decoders;
etching a plurality of cavities through the stack of layers, the plurality of cavities arranged in rows extending in a first horizontal direction and columns extending in a second horizontal direction;
and
depositing a conductive material in the plurality of cavities to form a first plurality of vias in a first subset of the plurality of cavities and a second plurality of vias in a second subset of the plurality of cavities, each of the first plurality of vias coupled with a respective access line decoder of the plurality of access line decoders, and each of the second plurality of vias electrically isolated from the plurality of access line decoders, and each of the second plurality of vias located between the first plurality of vias and a memory region in the first horizontal direction, the memory region comprising memory cells formed in the stack of layers.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 17/752,332Filed 24 May 2022
Granted: 12 Sep 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

G11C 7/18
Arrangements for writing information into, or reading information out from, a digital store: bit line organisation; Bit line lay-out
H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
G11C 7/1027
Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters: static column decode…
H10B 43/40
EEPROM devices comprising charge-trapping gate insulators: characterised by the peripheral circuit region