System and method for reading and writing memory management data through a non-volatile cell based register

A memory device, comprising:

• a plurality of memory cells accessible via a first plurality of row lines and a first plurality of column lines, wherein each memory cell of the plurality of memory cells comprises a ferroelectric capacitor;
• a decoder coupled with the plurality of memory cells;
• a sense component coupled with the plurality of memory cells;
• a peripheral circuit coupled with the decoder, the peripheral circuit comprising:
• a buffer coupled with the decoder;
• a counter coupled with the buffer;
• a first driver coupled with the counter;
• a second driver coupled with the first driver;
• a first controller coupled with the first driver and the second driver;
• and
• a latch unit array coupled with the first controller and the second driver, the latch unit array comprising a plurality of latch units addressable via a second plurality of row lines and a second plurality of column lines, wherein each latch unit of the plurality of latch units comprises a memory element comprising plurality of ferroelectric capacitors;
• and
• a second controller coupled with the plurality of memory cells via the decoder and the sense component, wherein the second controller is configured to access the plurality of memory cells.

An apparatus, comprising:

• a latch unit array comprising a plurality of latch units coupled with a first plurality of row lines and a first plurality of column lines, wherein each latch unit comprises a respective first memory element coupled with a first signal line and a second signal line, and a respective second memory element coupled with the first signal line and a third signal line, the respective first memory elements and second memory elements each comprising a respective plurality of ferroelectric memory cells, wherein the latch unit array is configured to:
• build, at a first time, respective second charges at the respective second memory elements based at least in part on respective first charges stored at the respective first memory elements and a first signal applied to the second signal line at the first time;
• and
• latch, at a second time after the first time, respective values associated with the respective second charges using one or more respective transistors of each latch unit.