Synchronous memory device with dual page and burst mode operations

A Synchronous memory device comprising:

• a plurality of addressable memory data storage cells arranged in rows and columns;
• a supply input;
• a ground input;
• an address input;
• a dat input/output;
• and
• a plurality of control signal inputs consisting essentially of:
• a write enable input;
• a byte enable input;
• a row address strobe input;
• a clock input for a clock signal;
• and
• a burst control (BC) input adapted to receive a BC signal, a first state of the BC signal enabling a column address circuit to receive a column address in response to the clock signal such that the memory operates in a non-burst mode where column address are provided externally, and a second state of the BC signal enabling the column address circuit to generate additional column addresses in response to the clock signal such that the memory operates in a burst mode, without a separate column address strobe (CAS) signal in both the first state and the second state.

An apparatus comprising:

• a burst access memory device adapted to receive a free running clock input signal, said burst access memory device comprising:
• a plurality of addressable memory data storage cells arranged in rows and columns;
• a row address strobe (RAS) input adapted to receive a RAS signal which enables a row address latch to receive a row address in response to the clock signal;
• a byte enable (BE) input adapted to receive a BE signal which enables the burst access memory to output data in a read cycle and to store data in a write cycle, the BE signal also selecting between an access cycle and a refresh cycle;
• a column address circuit;
• and
• a burst control (BC) input adapted to receive a BC signal, a first state of the BC signal enabling said column address circuit to receive a column address in response to the clock signal such that the memory operates in a non-burst mode where column address are provided externally, and a second state of the BC signal enabling said column address circuit to generate additional column addresses in response to the clock signal such that the memory operates in a burst mode, without a separate column address strobe (CAS) signal in both the first state and the second state.