US 5,263,003 A · Flash memory circuit and method of operation

Abstract

A memory circuit for storing words of data has two memory banks each formed by a plurality of memory devices connected in parallel. In a first mode, the memory circuit responds to an initial request for access and an address signal by reading data from a storage location in one of the memory banks. Subsequent requests for access to contiguous storage locations do not require an address signal, instead a control mechanism responds by generating an address to read data alternately from storage locations in the first and second memory banks. In a second mode, the memory circuit responds to every request for access to the memory circuit by enabling access to the first or second memory bank as indicated by an address which accompanied the request. The memory devices of a given bank are erased and programmed in parallel. However, when a given storage location is found to contain one or more bits that were not erased, another erase command is sent to only those memory devices associated with a bit that was not erased. Similarly, when a word of data has not been stored properly, only those memory devices which failed to store a bit are placed into the write state for another programming attempt.

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Claims19

Dependent claims

A memory circuit for storing words of digital data comprising:

a first means for receiving a storage location address;
a second means for receiving control signals requesting access to the memory circuit;
a means for exchanging data with an external device;
first and second memory banks each having a series of storage locations and being coupled to said means for exchanging data;
an address bus connected to said first and second memory banks;
means for controlling said first and second memory banks, having a first mode in which this latter means responds to an address and a request for access received respectively from said first and second means for receiving by reading data from a storage location in one of said memory banks, and thereafter generating addresses on said address bus to read data alternately from storage locations in said first and second memory banks in response to subsequent requests for access to the memory circuit, and having a second mode in which said means for controlling responds to an address and a request for access to the memory circuit by enabling only one of said first and second memory banks and thereafter generating addresses on said address bus to read information sequentially from storage locations in the one bank.

3 more elements

A memory circuit for storing multiple bit words of digital data comprising:

a first means for receiving control signals requesting access to the memory circuit;
first and second memory banks each having a series of storage locations;
an address but connected to said first and second memory banks;
a second means for receiving a storage location address consisting of a plurality of binary bits and providing a first address value and a second address value that is substantially equal to one-half the first address value;
an address generator coupled to said second means for receiving, and producing a sequence of output addresses in response to the second address value which indicates an initial output address of the sequence and applying the output addresses to said address bus when enabled by a control signal received by said memory circuit, otherwise said address generator applies the first address value to said address bus;
and
a means for controlling said address generator and said first and second memory banks, and in a first mode said means for controlling is responsive to each request in a series of requests for access to the memory circuit by reading stored data alternately from the first and second memory banks, and having a second mode in which said means for controlling responds each request in a series of requests for access to the memory circuit by enabling a same one of said first and second memory banks.

4 more elements

A method of erasing a memory circuit that includes a first bank of a plurality of memory devices coupled in parallel to form a set of storage locations, each memory device being responsive to an erase command by erasing a plurality of data storage areas in the device;

steps of said method comprising:
(a) issuing the erase command to every memory device in the first bank;
(b) then sequentially reading the contents of each storage location and determining whether every bit of the storage location has been erased;
and
(c) when a given storage location is found to contain a bit that was not erased, sending another erase command to only those memory devices associated with the bit that was not erased, and then reading the contents of the given storage location to determine whether every bit now has been erased.

2 more elements

Dependencies are inferred from the claim text.

Description10,415 words

Summary1,389 words

#The invention relates to solid state memory devices for storing digital data; and particularly to a class of such devices commonly referred to as flash memories.

#A flash memory is a non-volatile storage device which is based on erasable programmable read only memory (EPROM) and electrically erasable programmable read only memory (EEPROM) technologies. As such, these devices can be programmed in the equipment in which they are used by applying a programming-erasing voltage and executing an erasure procedure to set all of the bits in the device to a high logic level. Thereafter, another procedure is used to program the device with new data. It is predicted that flash-type devices will be used in many applications that today are implemented by EPROM, EEPROM, battery-backed static RAM and disk memory.

#Standard memories are commonly configured as interleaved banks of devices to obtain improved performance and faster access time. In this technique, two or more banks of identical memory devices are arranged in such a way that the requests for data from each one overlap, i.e. when one bank is delivering data, the other bank is preparing to deliver the next sequential item of data. In this way, slower, cheaper memory devices may be employed which none the less deliver high performance.

Brief description of the drawings6 figures

#FIG. 1 is a pictorial representation of a programmable controller;

#FIG. 2 is a schematic diagram of a system controller in FIG. 1 which uses a flash memory according to the present invention;

#FIG. 3 is a schematic diagram of the flash memory;

Detailed description8,935 words

#With initial reference to FIG. 1, a programmable controller 10 of the present invention is housed in a rack 12 which includes a series of slots that receive a plurality of printed circuit board modules. These functional modules connect to a mother board which extends along the back surface of the rack 12 to provide a backplane 11. The backplane 11 has a plurality of module connectors which are interconnected by a conductive pattern on the backplane. The backplane 11 provides a series of signal buses to which the modules connect. The rack 12 contains a power supply module 14, a system controller 16, a number of program execution processor modules 18 and a plurality of remote input/output (I/O) scanner modules 20, although only one scanner module is required. The remaining locations in rack 12 are empty and the slots are covered by blank plates until additional functional modules are to be inserted in these slots.

#Up to four remote I/O scanner modules 20 interface the controller 10 to external remote I/O racks 17 via serial I/O data links 15. Each remote I/O rack 17 has a plurality of local I/O modules 19 which are coupled to individual sensors and actuators on the controlled equipment. The local I/O modules 19 may take many forms and may provide D.C. inputs or outputs, A.C. inputs or outputs, analog inputs or outputs, and open or closed loop positioning modules, for example. The I/O racks 17 and networks 15 employ conventional interface and communication technology. The remote I/O rack 17 also contains an adapter module 26; such as the one described in U.S. Pat. No. 4,413,319, which controls the transmission of data via the I/O network 15 between the I/O modules 19 and the scanner modules 20.

#The system controller 16 is connected through cable 25 to a programming terminal 24, which is used to load the user programs into the programmable controller and configure its operation, as well as monitor system performance. The terminal 24 is a personal computer programmed to enable the user to develop the control programs on the terminal, which then are loaded into the programmable controller. Once the programs have been loaded into the programmable controller 10 and their operation debugged, the terminal 24 may be disconnected from the system controller 16 if operational monitoring is not required. The system controller 16 also may be connected to a local area network (LAN) 28, over which data and programming instructions can be received and status information and report data sent to a host computer. This enables a host computer or central terminal to program and control the operation of a plurality of programmable controllers on a factory floor.

Facts

Application

07/790,833Filed 12 Nov 1991

Granted

16 Nov 1993

Term ended

12 Nov 2011

Estimated · how

Pre-1995 term; greater of 17 years from grant or 20 years from filing when eligible. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification5 codes

G11C 7/1027
Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters: static column decode…
G11C 7/1045
Read-write modes for single port memories, i.e. having either a random port or a serial port: read-write mode select circuits
G11C 16/08
Auxiliary circuits, e.g. for writing into memory: address circuits; Decoders; Word-line control circuits
G11C 16/26
Auxiliary circuits, e.g. for writing into memory: sensing or reading circuits; Data output circuits

Flash memory circuit and method of operation

Life of this patent

Flash memory circuit and method of operation

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims19

Description10,415 words

Drawings

Classification5 codes

Life of this patent

Description10,415 words