G11C 29/022
In i/o circuitry
Official title: {in I/O circuitry}
G11C29/022 (In i/o circuitry) appears on 1,441 US grants and 1,526 published applications in this corpus.
Search patents in G11C- Granted patents
- 1,441
- Published applications
- 1,526
- Assignees
- 230
- Inventors
- 2,145
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1993 | 2 | 0 |
| 1994 | 2 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 1 | 0 |
| 1998 | 1 | 0 |
| 1999 | 0 | 0 |
| 2000 | 4 | 0 |
| 2001 | 1 | 1 |
| 2002 | 5 | 5 |
| 2003 | 4 | 11 |
| 2004 | 8 | 27 |
| 2005 | 17 | 30 |
| 2006 | 25 | 40 |
| 2007 | 33 | 58 |
| 2008 | 44 | 56 |
| 2009 | 55 | 54 |
| 2010 | 41 | 33 |
| 2011 | 50 | 42 |
| 2012 | 39 | 48 |
| 2013 | 55 | 42 |
| 2014 | 52 | 58 |
| 2015 | 61 | 83 |
| 2016 | 79 | 41 |
| 2017 | 62 | 64 |
| 2018 | 66 | 58 |
| 2019 | 88 | 102 |
| 2020 | 101 | 76 |
| 2021 | 85 | 91 |
| 2022 | 93 | 121 |
| 2023 | 113 | 130 |
| 2024 | 90 | 115 |
| 2025 | 107 | 72 |
| 2026 | 57 | 68 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
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- Memory device, memory device including memory die stack, and wafer-level testing method for semiconductor chip1 Oct 2026US 2026/0301833 A1Samsung Electronics Co., Ltd.
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Most cited
By later US patents
- Method and apparatus for coordinating memory operations among diversely-located memory components165US 6,675,272 B2Rambus Inc. · 2004
- Method and apparatus for evaluating and optimizing a signaling system146US 7,490,275 B2Rambus Inc. · 2009
- System and method for simulating an aspect of a memory circuit133US 7,609,567 B2Metaram, Inc. · 2009
- Testing timing parameters of high speed integrated circuit devices129US 5,268,639 ARambus Inc. · 1993
- Memory systems and memory modules112US 8,060,774 B2Google Inc. · 2011