Integrated circuit and method of operating same

An integrated circuit, comprising:

• a first memory cell array;
• a second memory cell array;
• a control circuit coupled to the first memory cell array and the second memory cell array;
• a first set of sense amplifiers coupled to the first memory cell array;
• a second set of sense amplifiers coupled to the second memory cell array;
• a first error correction code (ECC) circuit configured to store a first set of ECC check bits;
• a second ECC circuit configured to store a second set of ECC check bits;
• a first ECC encoder/decoder circuit configured to generate the first set of ECC check bits based on a first set of data stored in the first memory cell array;
• and
• a second ECC encoder/decoder circuit configured to generate the second set of ECC check bits based on a second set of data stored in the second memory cell array,
• wherein the first ECC circuit and the second ECC circuit are configured to correct at least a first number of errors in the first set of data and the second set of data based on the first set of ECC check bits and the second set of ECC check bits;
• wherein the first ECC circuit comprises:
• a first ECC memory cell array;
• a second ECC memory cell array;
• a third ECC memory cell array;
• a first sense amplifier coupled to the first ECC memory cell array;
• a second sense amplifier coupled to the second ECC memory cell array;
• and
• a third sense amplifier coupled to the third ECC memory cell array.

A method of operating an integrated circuit, the method comprising:

• performing a programming operation of a first set of memory cells, the performing the programming operation of the first set of memory cells comprising:
• storing a first set of data in a first memory cell array and a second set of data in a second memory cell array;
• generating a first set of check bits in response to the first set of data and a second set of check bits in response to the second set of data;
• and
• storing the first set of check bits in a first ECC memory cell array, and the second set of check bits in a second ECC memory cell array, the first ECC memory cell array and the second ECC memory cell array being part of a first ECC circuit;
• performing a read operation of the first set of memory cells;
• and
• correcting read data from the first or second memory cell array in response to determining that data read from the first or second memory cell array contains an error based on the first set of check bits and the second set of check bits;
• wherein the first ECC circuit comprises:
• the first ECC memory cell array;
• the second ECC memory cell array;
• a third ECC memory cell array;
• a first sense amplifier coupled to the first ECC memory cell array;
• a second sense amplifier coupled to the second ECC memory cell array;
• and
• a third sense amplifier coupled to the third ECC memory cell array.