System and method for simulating an aspect of a memory circuit
AssigneeMetaram, Inc.
InventorsSuresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
Life of this patent
Estimating the term…
Abstract
A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. In accordance with various embodiments, such aspect may include a signal, a capacity, a timing, and/or a logical interface.
Claims28
A sub-system, comprising:
- an interface circuit in communication with a plurality of memory circuits and a system, the interface circuit operable to interface the memory circuits and the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits;
- wherein the at least one aspect is selected from the group consisting of a signal, a capacity, a timing, and a logical interface;
- wherein the interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit with a first memory capacity that is greater than a second memory capacity of at least one of the plurality of memory circuits.
The sub-system of claim I, wherein the memory circuits each include dynamic random access memory (DRAM).
A method, comprising:
- interfacing a plurality of memory circuits and a system;
- and
- simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits;
- wherein the at least one aspect is selected from the group consisting of a signal, a capacity, a timing, and a logical interfaces;
- wherein an interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit with a first memory capacity that is greater than a second memory capacity of at least one of the plurality of memory circuits.
A sub-system, comprising:
- an interface circuit in communication with a plurality of memory circuits and a system, the interface circuit operable to interface the memory circuits and the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits;
- wherein the interface circuit interfaces a majority of address or control signals of the memory circuits;
- wherein the interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit with a first memory capacity that is greater than a second memory capacity of at least one of the plurality of memory circuits.
A system, comprising:
- an interface circuit for interfacing a plurality of memory circuits and the system, and for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits;
- wherein the at least one aspect is selected from the group consisting of a signal, a capacity, a timing, and a logical interface;
- wherein the interface circuit is operable to interface the memory Circuits and the system for simulating at least one memory circuit with a first CAS latency that is longer than a second CAS latency of at least one of the plurality of memory circuits.
Dependencies are inferred from the claim text.