Block family error avoidance bin scans after memory device power-on
AssigneeMicron Technology, Inc.
InventorGuang Hu
Life of this patent
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Abstract
A method includes identifying a read level offset assigned to a final bin in a scan order defined for a set of bins, identifying a set of bit error metric values by performing, using the read level offset, a scan operation with respect to a block of memory cells of the memory array, determining whether a final bit error metric value of the set of bit error metric values is greater than or equal to a threshold value, in response to determining that the final bit error metric value is greater than or equal to the threshold value, identifying a lowest bit error metric value of the set of bit error metric values, and selecting, from the set of bins, a bin having an assigned read level offset corresponding to the lowest bit error metric value.
Claims20
A memory device comprising:
- a memory array;
- and
- a controller, operatively coupled to the memory array, configured to:
- identify a read level offset assigned to a final bin in a scan order defined for a set of bins, wherein each bin of the set of bins is associated with a respective block family comprising one or more blocks of memory cells that have been programmed within a certain time window;
- identify a set of bit error metric values by performing, using the read level offset, a scan operation with respect to a block of memory cells of the memory array;
- determine whether a final bit error metric value of the set of bit error metric values is greater than or equal to a threshold value;
- in response to determining that the final bit error metric value is greater than or equal to the threshold value, identify a lowest bit error metric value of the set of bit error metric values;
- and
- select, from the set of bins, a bin having an assigned read level offset corresponding to the lowest bit error metric value.
A method comprising:
- identifying, by a processing device, a read level offset assigned to a final bin in a scan order defined for a set of bins, wherein each bin of the set of bins is associated with a respective block family comprising one or more blocks of memory cells that have been programmed within a certain time window;
- identifying, by the processing device, a set of bit error metric values by performing, using the read level offset, a scan operation with respect to a block of memory cells of a memory array;
- determining, by the processing device, whether a final bit error metric value of the set of bit error metric values is greater than or equal to a threshold value;
- in response to determining that the final bit error metric value is greater than or equal to the threshold value, identifying, by the processing device, a lowest bit error metric value of the set of bit error metric values;
- and
- selecting, by the processing device from the set of bins, a bin having an assigned read level offset corresponding to the lowest bit error metric value.
A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
- identifying a read level offset assigned to a final bin in a scan order defined for a set of bins, wherein each bin of the set of bins is associated with a respective block family comprising one or more blocks of memory cells that have been programmed within a certain time window;
- identifying a set of bit error metric values by performing, using the read level offset, a scan operation with respect to a block of memory cells of a memory array;
- determining whether a final bit error metric value of the set of bit error metric values is greater than or equal to a threshold value;
- in response to determining that the final bit error metric value is greater than or equal to the threshold value, identifying a lowest bit error metric value of the set of bit error metric values;
- and
- selecting, from the set of bins, a bin having an assigned read level offset corresponding to the lowest bit error metric value.
Dependencies are inferred from the claim text.