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US 5,268,639 AGranted
Testing timing parameters of high speed integrated circuit devices
AssigneeRambus Inc.
InventorsJames A. Gasbarro, Mark A. Horowitz
Life of this patent
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Abstract
A method and apparatus for testing input and output parameters for high speed integrated circuit devices. An integrated circuit tester generates a receive clock and a transmit clock using a pair of pre-selected output pins. The integrated circuit tester adjusts the phase relation between the transmit clock and the receive clock. Special circuitry within the device under test compares input and output data to detect errors.
Claims5
A method for testing clock to output time for an integrated circuit device, comprising the steps of:
- (a) storing an output parameter test pattern in the integrated circuit device;
- (b) generating a receive clock and a transmit clock using a pair of output pins of an integrated circuit tester;
- (c) coupling the transmit clock to a transmit clock input of the integrated circuit device, such that the transmit clock causes the integrated circuit device to generate an output data bit stream by transmitting the output parameter test pattern over a bus data pin;
- (d) coupling the receive clock to a receive clock input of the integrated circuit device, such that the receive clock causes the integrated circuit device to generate an input data pattern by sampling the output data bit stream on the bus data pin;
- (e) adjusting the phase relation between the transmit clock and the receive clock, and comparing the input data pattern with the output data bit stream to determine the clock to output time.
2 more elements
Dependencies are inferred from the claim text.