Memory systems and memory modules
AssigneeGoogle Inc.
InventorsMichael John Sebastian Smith, Suresh Natarajan Rajan
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Abstract
One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems.
Claims51
A memory module, comprising:
- at least one memory chip;
- and
- a first intelligent chip coupled to the at least one memory chip and adapted to be coupled to a memory controller, wherein the first intelligent chip is configured to implement at least a part of a reliability and serviceability (RAS) feature;
- and
- a second intelligent chip coupled to the at least one memory chip and adapted to be coupled to the memory controller, and a sideband bus that couples the first intelligent chip to the second intelligent chip, wherein the second intelligent chip is configured to transmit a signal to the first intelligent chip to turn off an output buffer associated with the first intelligent chip.
Dependencies are inferred from the claim text.