G11C 16/102
External programming circuits
Official title: {External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators}
G11C16/102 (External programming circuits) appears on 1,578 US grants and 1,712 published applications in this corpus.
Search patents in G11C- Granted patents
- 1,578
- Published applications
- 1,712
- Assignees
- 411
- Inventors
- 2,643
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1978 | 1 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 1 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 1 | 0 |
| 1987 | 1 | 0 |
| 1988 | 7 | 0 |
| 1989 | 2 | 0 |
| 1990 | 3 | 0 |
| 1991 | 1 | 0 |
| 1992 | 1 | 0 |
| 1993 | 4 | 0 |
| 1994 | 15 | 0 |
| 1995 | 20 | 0 |
| 1996 | 33 | 0 |
| 1997 | 21 | 0 |
| 1998 | 31 | 0 |
| 1999 | 18 | 0 |
| 2000 | 32 | 0 |
| 2001 | 26 | 14 |
| 2002 | 37 | 34 |
| 2003 | 32 | 32 |
| 2004 | 30 | 50 |
| 2005 | 40 | 66 |
| 2006 | 40 | 69 |
| 2007 | 43 | 69 |
| 2008 | 54 | 41 |
| 2009 | 42 | 41 |
| 2010 | 28 | 39 |
| 2011 | 52 | 37 |
| 2012 | 34 | 18 |
| 2013 | 37 | 21 |
| 2014 | 33 | 45 |
| 2015 | 48 | 35 |
| 2016 | 42 | 27 |
| 2017 | 20 | 21 |
| 2018 | 30 | 33 |
| 2019 | 36 | 36 |
| 2020 | 34 | 21 |
| 2021 | 23 | 22 |
| 2022 | 49 | 141 |
| 2023 | 114 | 221 |
| 2024 | 177 | 210 |
| 2025 | 168 | 193 |
| 2026 | 117 | 176 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Re-driving data to a sub-block during programming of multiple sub-blocks6 Oct 2026US 12,755,791 B2Micron Technology, Inc.
- Using non-segregated cells as drain-side select gates for sub-blocks in a memory device6 Oct 2026US 12,755,792 B2Micron Technology, Inc.
- Memory array and methods of operation6 Oct 2026US 12,755,793 B2Microchip Technology Incorporated
- Memory, operation method thereof, and memory system6 Oct 2026US 12,755,801 B2Yangtze Memory Technologies Co., Ltd.
- Managing allocation of blocks across planes in a memory sub-system29 Sep 2026US 12,749,537 B2Micron Technology, Inc.
- Lateral charge migration handling on edge wordlines of a memory device in a memory sub-system8 Oct 2026US 2026/0311764 A1Micron Technology, Inc.
- Semiconductor structure, method of operating thereof, and semiconductor device8 Oct 2026US 2026/0311765 A1Yangtze Memory Technologies Holding Co., Ltd.
- Bias voltage control for sub-block groups in a memory device8 Oct 2026US 2026/0311766 A1Micron Technology, Inc.
- Drift compensation for codewords in memory8 Oct 2026US 2026/0311767 A1Micron Technology, Inc.
- Resample start voltage for calibration in a program operation improvement8 Oct 2026US 2026/0311768 A1Micron Technology, Inc.
Most cited
By later US patents
- Flash memory mass storage architecture incorporating wear leveling technique without using cam cells376US 5,485,595 ACirrus Logic, Inc. · 1996
- Method of and architecture for controlling system data with automatic wear leveling in a semiconductor non-volatile mass storage memory352US 5,835,935 ALexar Media, Inc. · 1998
- Microcontroller with programmable embedded flash memory348US 6,009,496 AWinbond Electronics Corp. · 1999
- Flash memory mass storage architecture322US 5,388,083 ACirrus Logic, Inc. · 1995
- Partial block data programming and reading operations in a non-volatile memory321US 6,763,424 B2SanDisk Corporation · 2004