Flash memory mass storage architecture

A non-volatile semiconductor mass storage device comprising:

• a. a plurality of non-volatile storage blocks, wherein each block is selectively programmable to store data and is selectively erasable and further wherein each block has a finite number of erase cycle lifetimes;
• b. a plurality of counters, one counter for each block, to count each time its associated block is erased, wherein a programmable maximum value is applied to all the blocks;
• c. a plurality of erase inhibit flags, each flag having a set condition and an unset condition, one flag for each block, wherein the flag for a block having a count value equal to the maximum value is set to prevent further erasing of that block;
• d. a controller to switch data in a block having a relatively small count value into a block having the maximum value;
• and
• e. an erase element to clear all counters and all flags once all flags are set.

A method of maintaining parity of erase cycles amongst storage blocks in a non-volatile semiconductor mass storage device having a plurality of non-volatile storage blocks, wherein each block is selectively programmable to store data and is selectively erasable and further wherein each block has a finite number of erase cycle lifetimes, the method comprising;

• a. counting and maintaining a count value for each block representing each time it is erased;
• b. setting a predetermined maximum value;
• c. preventing an erase cycle from being performed on a block having a count value equal to the maximum value;
• d. switching data from a block having a smallest count value into a block having the maximum value;
• and
• e. erasing the count values once all blocks have been erased the maximum value of times.