Using non-segregated cells as drain-side select gates for sub-blocks in a memory device
AssigneeMicron Technology, Inc.
InventorAaron S. Yip
Life of this patent
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Abstract
Control logic in a memory device receives a request to program data to a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and identifies a first sub-block of the plurality of sub-blocks to be programmed with at least a portion of the data. The control logic further causes a plurality of control signals to be applied to a plurality of logical select gate layers positioned at a drain-side of the block to activate the first sub-block, and causes a program signal to be applied to a selected wordline of the block to program at least the portion of the data to a memory cell in the first sub-block and associated with the selected wordline.
Claims20
A memory device comprising:
- a memory array;
- and
- control logic, operatively coupled with the memory array, to perform operations comprising:
- causing a plurality of control signals to be applied to a plurality of logical select gate layers positioned at a drain-side of a segment of the memory array to activate a first sub-portion of the segment;
- and
- causing a program signal to be applied to a selected wordline of the segment to program data to a memory cell in the first sub-portion of the segment and associated with the selected wordline.
A method comprising:
- causing a plurality of control signals to be applied to a plurality of logical select gate layers positioned at a drain-side of a segment of a memory array of a memory device to activate a first sub-portion of the segment;
- and
- causing a program signal to be applied to a selected wordline of the segment to program data to a memory cell in the first sub-portion of the segment and associated with the selected wordline.
A memory device comprising:
- a memory array comprising a segment, the segment comprising a plurality of wordlines and a number of sub-portions each comprising a plurality of memory cells associated with the plurality of wordlines,
- wherein the memory array further comprises a number of logical select gate layers positioned at a drain-side of the segment to selectively activate individual sub-portions of the segment responsive to received control signals.
Dependencies are inferred from the claim text.