G06F 9/3888
Controlled by a single instruction for multiple threads [simt] in parallel
Official title: {controlled by a single instruction for multiple threads [SIMT] in parallel}
G06F9/3888 (Controlled by a single instruction for multiple threads [simt] in parallel) appears on 1,142 US grants and 1,324 published applications in this corpus.
Search patents in G06F- Granted patents
- 1,142
- Published applications
- 1,324
- Assignees
- 146
- Inventors
- 1,798
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1984 | 1 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 0 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 1 | 0 |
| 1996 | 0 | 0 |
| 1997 | 2 | 0 |
| 1998 | 9 | 0 |
| 1999 | 5 | 0 |
| 2000 | 4 | 0 |
| 2001 | 5 | 5 |
| 2002 | 2 | 5 |
| 2003 | 2 | 4 |
| 2004 | 2 | 2 |
| 2005 | 5 | 20 |
| 2006 | 5 | 27 |
| 2007 | 8 | 27 |
| 2008 | 28 | 37 |
| 2009 | 29 | 24 |
| 2010 | 32 | 21 |
| 2011 | 32 | 45 |
| 2012 | 35 | 33 |
| 2013 | 35 | 29 |
| 2014 | 39 | 74 |
| 2015 | 32 | 47 |
| 2016 | 64 | 88 |
| 2017 | 81 | 76 |
| 2018 | 71 | 79 |
| 2019 | 78 | 79 |
| 2020 | 94 | 78 |
| 2021 | 87 | 89 |
| 2022 | 63 | 116 |
| 2023 | 82 | 94 |
| 2024 | 92 | 60 |
| 2025 | 76 | 108 |
| 2026 | 41 | 57 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Cache structure and utilization6 Oct 2026US 12,754,876 B2Intel Corporation
- Systems, methods, and apparatuses for heterogeneous computing29 Sep 2026US 12,748,618 B2Intel Corporation
- Streaming wave coalescer circuit15 Sep 2026US 12,737,190 B2Advanced Micro Devices, Inc.
- Systems and methods for updating memory side caches in a multi-GPU configuration15 Sep 2026US 12,737,317 B2Intel Corporation
- Cache structure and utilization15 Sep 2026US 12,737,318 B2Intel Corporation
- Performing frequency allocation in parallel8 Oct 2026US 2026/0312700 A1NVIDIA Corporation
- System, Method, and Computer Program Product for Processing Inference Requests to Execute a Machine-Learning Model24 Sep 2026US 2026/0288470 A1Visa International Service Association
- Chiplet-integrated machine learning accelerators24 Sep 2026US 2026/0288661 A1Advanced Micro Devices, Inc.
- Coordinate thread execution in multi-cluster architectures10 Sep 2026US 2026/0267654 A1QUALCOMM Incorporated
- Apparatus and method for scheduling inference tasks10 Sep 2026US 2026/0267655 A1Intel Corporation
Most cited
By later US patents
- Vector processor system420US 8,356,144 B22013
- Dynamic multi-mode parallel processing array390US 5,475,856 AInternational Business Machines Corporation · 1995
- Sparse convolutional neural network accelerator339US 10,891,538 B2NVIDIA Corporation · 2021
- Method and apparatus for executing multiple instruction streams in a digital processor with multiple data paths274US 6,272,616 B1Agere Systems Guardian Corp. · 2001
- Coordination and synchronization of an asymmetric, single-chip, dual multiprocessor225US 5,978,838 ASamsung Electronics Co., Ltd. · 1999