US 5,978,838 A · Coordination and synchronization of an asymmetric, single-chip, dual multiprocessor

Abstract

An integrated multiprocessor architecture simplifies synchronization of multiple processing units. The multiple processing units constitute a general-purpose or control processor and a vector processor which has a single-instruction-multiple-data (SIMD) architecture so that multiple parallel processing units in the vector processor all complete an instruction simultaneously and do not require software synchronization. The control control processor controls the vector processor and creates a fork in a program flow by starting the vector processor. An instruction set for the control processor includes special instructions that enable the control processor to access registers of the vector processor, start or halt execution by the vector processor, and test flags written by the vector processor to indicate completion of tasks. The two processors then execute separate program threads in parallel until the control processor stops the vector processor, an exception is encountered, or the vector processor completes its program thread and enters an idle state. An instruction set for the vector processor includes special instructions that interrupt the first processor to indicate a task is complete. A register coupled to and accessible by both processors stores a state bit indicating whether the vector processor is running or idle. The control processor can synchronize the separate program threads by executing a loop which polls the state bit. When the state bit indicates the vector processor is idle, the general-purpose processor can process results from the vector processor and restart the vector processor.

Claims15

Dependent claims

An integrated multiprocessor comprising:

a first processor;
a second processor operable in a first state to execute a sequence of program instructions, and operable in a second state where the second processor is idle;
and
a register coupled to enable both the first processor and the second processor to access the register, the register storing a value controls whether the second processor is in the first or second state wherein:
the first processor implements a first instruction set including a first instruction that when executed by the first processor starts the second processor executing the sequence of program instructions and a second instruction that when executed by the first processor idles the second processor;
and
the second processor implements the second instruction set lacking instructions that allow the second processor to start or halt execution by the first process and including a third instruction that generates an interrupt to the first processor, the interrupt indicating that the second processor has completed an operation that the first processor started the second processor executing.

4 more elements

Dependencies are inferred from the claim text.

Coordination and synchronization of an asymmetric, single-chip, dual multiprocessor

Life of this patent

Coordination and synchronization of an asymmetric, single-chip, dual multiprocessor

Life of this patent

Abstract

Claims15