US 5,475,856 A · Dynamic multi-mode parallel processing array · patentgrep

Loading patent…

Abstract

A Parallel RISC computer system is provided by a multi-mode dynamic multi-mode parallel processor array with one embodiment illustrating a tightly coupled VLSI embodiment with an architecture which can be extended to more widely placed processing elements through the interconnection network which couples multiple processors capable of MIMD mode processing to one another with broadcast of instructions to selected groups of units controlled by a controlling processor. The coupling of the processing elements logic enables dynamic mode assignment and dynamic mode switching, allowing processors operating in a SIMD mode to make maximum memory and cycle time usage. On and instruction by instruction level basis, modes can be switched from SIMD to MIMD, and even into SISD mode on the controlling processor for inherently sequential computation allowing a programmer or complier to build a program for the computer system which uses the optimal kind of parallelism (SISD, SIMD, MIMD). Furthermore, this execution, particularly in the SIMD mode, can be set up for running applications at the limit of memory cycle time. With the ALLNODE switch and alternatives paths a system can be dynamically achieved in a few cycles for many many processors. Each processing element and memory and has MIMD capability the processor's an instruction register, condition register and program counter provide common resources which are used in MIMD and SIMD. The program counter become a base register in SIMD mode.

Claims37

Dependent claims

A dynamic multi-mode parallel processing array, comprising:

a plurality of processors, each processor having a control unit for decoding and executing instructions of an instruction set, a data flow unit and a local memory, each of said control units having an instruction register, a program counter, a condition code register and a parallel mode bit (PMB), the PMB indicating whether the processor obtains instructions from a controlling processor or from said local memory;
an interconnection path between the instruction registers of the processors;
the instruction set having a plurality of instructions, each instruction having a parallel execution type bit (PET) that is used in conjunction with the PMB by the control unit to determine whether an instruction should be executed, the instruction set having a switch mode instruction for changing the PMB bit of a processor executing the instruction;
the processors organized into one or more groups, each group having a processor configured as the controlling processor, wherein any processor in the plurality of processors can be dynamically configured as the controlling processor, the controlling processor enabling the processors of a group to operate in a MIMD or SIMD mode, and to switch modes dynamically;
and
when a group of processors are operating in SIMD mode the controlling processor provides instructions to the instruction registers of the other processors in the group, each instruction provided via the interconnection path when the controlling processor fetches the instruction;
wherein a controlling processor of a group of processors fetches instructions, and wherein other processors in the group latch into their instruction registers each instruction as the controlling processor fetches it, such that at the end of the instruction fetch all other processors have in their instruction register the fetched instruction;
and
wherein the instruction set includes instructions which modify a processor's program counter to function as a base register, including one or more of the following instructions:
a "Jump" instruction which when executed in a processor operating in SIMD mode sets the processor's program counter to a value provide with the jump instruction;
and
a "Load Immediate" instruction which when executed in a processor operating in SIMD mode loads a register with the contents of the processors' local memory, at the address specified by the processor's program counter and then increments the program counter.

9 more elements

A dynamic multi-mode parallel processing array, comprising:

a plurality of processors, each processor having a control unit for decoding and executing instructions of an instruction set, a data flow unit and a local memory, each of said control units having an instruction register, a program counter, a condition code register and a parallel mode bit (PMB), the PMB indicating whether the processor obtains instructions from a controlling processor or from said local memory;
an interconnection path between the instruction registers of the processors;
the instruction set having a plurality of instructions, each instruction having a parallel execution type bit (PET) that is used in conjunction with the PMB by the control unit to determine whether an instruction should be executed, the instruction set having a switch mode instruction for changing the PMB bit of a processor executing the instruction;
the processors organized into one or more groups, each group having a processor configured as the controlling processor, wherein any processor in the plurality of processors can be dynamically configured as the controlling processor, the controlling processor enabling the processors of a group to operate in a MIMD or SIMD mode, and to switch modes dynamically;
and
when a group of processors are operating in SIMD mode the controlling processor provides instructions to the instruction registers of the other processors in the group, each instruction provided via the interconnection path when the controlling processor fetches the instruction;
wherein a group of processors operating in SIMD mode switch to MIMD mode when the controlling processor provides each processor in the group with the switch mode instruction whereby each processor begins fetching instructions from its local memory;
and
wherein the processors can communicate with each other using a load instruction to send and a store instruction to receive, said instructions containing an address which is used as a processor address on the interconnection path of the processor to communicate with, wherein the processor stalls until the communication takes place.

6 more elements

A dynamic multi-mode parallel processing array, comprising:

a plurality of processors, each processor having an control unit for decoding and executing instructions of an instruction set, a data flow unit and a local memory, each of said control units having an instruction register, a program counter, a condition code register and a parallel mode bit (PMB), the PMB indicating whether the processor obtains instructions from a controlling processor or from said local memory;
an interconnection path between the instruction registers of the processors;
the instruction set having a plurality of instructions, each instruction having a parallel execution type bit (PET) that is used in conjunction with the PMB by the control unit to determine whether an instruction should be executed, the instruction set having a switch mode instruction for changing the PMB bit of a processor executing the instruction;
the processors organized into one or more groups, each group having a processor configured as the controlling processor, wherein any processor in the plurality of processors can be dynamically configured as the controlling processor, the controlling processor enabling the processors of a group to operate in a MIMD or SIMD mode, and to switch modes dynamically;
and
when a group of processors are operating in SIMD mode the controlling processor provides instructions to the instruction registers of the other processors in the group, each instruction provided via the interconnection path when the controlling processor fetches the instruction;
wherein a group of processors operating in SIMD mode switch to MIMD mode when the controlling processor provides each processor in the group with the switch mode instruction whereby each processor begins fetching instructions from its local memory;
and
wherein a switch mode instruction executed by a first processor causes the first processor to stall and use an address provided by the switch mode instruction as a key back to the controlling processor, the controller processor can then execute a switch mode instruction with an "address" which matches the key, and causes the first processor to leave the stall and resume tracking the controlling processor's instructions.

6 more elements

A dynamic multi-mode parallel processing array, comprising:

a plurality of processors, each processor having a control unit able to decode and execute instructions of an instruction set, a data flow unit and a local memory, each control unit having an instruction register, a program counter, a condition code register and a parallel mode bit (PMB), the PMB indicating whether the processor obtains instructions from a controlling processor or from local memory;
an interconnection path between the instruction registers of the processors;
the instruction set having a plurality of instructions, each instruction having a parallel execution type bit (PET) that is used in conjunction with the PMB by the control unit to determine whether an instruction should be executed, the instruction set having a switch mode instruction for changing the PMB bit of a processor executing the instruction;
the processors organized into one or more groups, each group having a processor configured as the controlling processor, wherein any processor in the plurality of processors can be dynamically configured as the controlling processor, the controlling processor enabling the processors of a group to operate in a MIMD or SIMD mode, and to switch modes dynamically;
and
when a group of processors are operating in SIMD mode the controlling processor provides instructions to the instruction registers of the other processors in the group, each instruction provided via the interconnection path when the controlling processor fetches the instruction;
wherein a group of processors operating in SIMD mode switch to MIMD mode when the controlling processor provides each processor in the group with the switch mode instruction whereby each processor begins fetching instructions from its local memory;
and
wherein a variable subset of processors operating in MIMD mode execute switch mode instructions that cause the variable subset of processors to operate in SIMD mode while those processors that are not part of the variable subset continue operating in MIMD mode.

6 more elements

A dynamic multi-mode parallel processing array, comprising:

a plurality of processors, each processor having a control unit for decoding and executing instructions of an instruction set, a data flow unit and a local memory, each of said control units having an instruction register, a program counter, a condition code register and a parallel mode bit (PMB), the PMB indicating whether the processor obtains instructions from a controlling processor or from said local memory;
an interconnection path between the instruction registers of the processors;
the instruction set having a plurality of instructions, each instruction having a parallel execution type bit (PET) that is used in conjunction with the PMB by the control unit to determine whether an instruction should be executed, the instruction set having a switch mode instruction for changing the PMB bit of a processor executing the instruction;
the processors organized into one or more groups, each group having a processor configured as the controlling processor, wherein any processor in the plurality of processors can be dynamically configured as the controlling processor, the controlling processor enabling the processors of a group to operate in a MIMD or SIMD mode, and to switch modes dynamically;
and
when a group of processors are operating in SIMD mode the controlling processor provides instructions to the instruction registers of the other processors in the group, each instruction provided via the interconnection path when the controlling processor fetches the instruction;
and
wherein the instruction set provides instructions where all memory references for data are performed via LOAD and STORE instructions, and where addressing for data accesses is a base plus displacement, and where addition and index register updates are applied after a memory operation has begun, as a post address update;
and wherein all instructions that perform computational operations are register to register, and said processors execute instructions in one or more execution cycles without need of memory references.

6 more elements

A dynamic multi-mode parallel processing array, comprising:

a plurality of processors, each processor having a control unit for decoding and executing instructions of an instruction set, a data flow unit and a local memory, each of said control units having an instruction register, a program counter, a condition code register and a parallel mode bit (PMB), the PMB indicating whether the processor obtains instructions from a controlling processor or from said local memory;
an interconnection path between the instruction registers of the processors;
the instruction set having a plurality of instructions, each instruction having a parallel execution type bit (PET) that is used in conjunction with the PMB by the control unit to determine whether an instruction should be executed, the instruction set having a switch mode instruction for changing the PMB bit of a processor executing the instruction;
the processors organized into one or more groups, each group having a processor configured as the controlling processor, wherein any processor in the plurality of processors can be dynamically configured as the controlling processor, the controlling processor enabling the processors of a group to operate in a MIMD or SIMD mode, and to switch modes dynamically;
and
when a group of processors are operating in SIMD mode the controlling processor provides instructions to the instruction registers of the other processors in the group, each instruction provided via the interconnection path when the controlling processor fetches the instruction
wherein a controlling processor of a group of processors fetches instructions, and wherein other processors in the group latch into their instruction registers each instruction as the controlling processor fetches it, such that at the end of the instruction fetch all other processors have in their instruction register the fetched instruction;
and
wherein after latching the fetched instruction each processor looks at its PMB and the PET obtained from the fetched instruction to determine whether to execute the fetched instruction, executing the fetched instruction accordingly.

6 more elements

A dynamic multi-mode parallel processing array, comprising:

a plurality of processors, each processor having a control unit for decoding and executing instructions of an instruction set, a data flow unit and a local memory, each of said control units having an instruction register, a program counter, a condition code register and a parallel mode bit (PMB), the PMB indicating whether the processor obtains instructions from a controlling processor or from said local memory;
an interconnection path between the instruction registers of the processors;
the instruction set having a plurality of instructions, each instruction having a parallel execution type bit (PET) that is used in conjunction with the PMB by the control unit to determine whether an instruction should be executed, the instruction set having a switch mode instruction for changing the PMB bit of a processor executing the instruction;
the processors organized into one or more groups, each group having a processor configured as the controlling processor, wherein any processor in the plurality of processors can be dynamically configured as the controlling processor, the controlling processor enabling the processors of a group to operate in a MIMD or SIMD mode, and to switch modes dynamically on an instruction-by, instruction basis;
and
when a group of processors are operating in SIMD mode the controlling processor provides instructions to the instruction registers of the other processors in the group, each instruction provided via the interconnection path when the controlling processor fetches the instruction;
and
wherein the PMB indicates SIMD and MIMD modes and the PET indicates local and array operations of the associated processor.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/324,295Filed 17 Oct 1994 · continuation
Priority: 27 Nov 1991
Granted: 12 Dec 1995
Term ends: Not estimatedThe source records don’t support an estimate.

Classification27 codes

G06F 9/3891
Controlled by multiple instructions, e.g. MIMD, decoupled access or execute: organised in groups of units sharing resources, e.g. clusters
G06F 7/483
Using non-contact-making devices, e.g. tube, solid state device; using unspecified devices: computations with numbers represented by a non-linear…
G06F 9/30
Using stored programs, i.e. using an internal store of processing equipment to receive or retain programs: arrangements for executing machine…
G06F 9/30036
To perform operations on data operands: instructions to perform operations on packed data, e.g. vector, tile or matrix operations

Family

Serial798,788Parent of this continuation · filed 27 Nov 1991
US 5,475,856 AThis patent

From the US filing history. Foreign family members aren’t listed.

Timeline

Citations

Open elsewhere