Streaming wave coalescer circuit

A streaming wave coalescer (SWC) circuit comprising:

• an insert wave memory configured to receive wave data comprising a plurality of threads from a first wave and a second wave;
• a first bin configured to store state values of threads associated with a first hard key from the first wave and the second wave, wherein a third wave is formed using the first bin comprising:
• a first subset of threads of the first wave based on the first subset of threads corresponding to a first sort key;
• and
• a second subset of threads of the second wave based on the second subset of threads corresponding to the first sort key;
• a second bin configured to store state values of threads associated with a second hard key, the second bin being different from the first bin;
• and
• an emit wave circuit configured to emit the third wave for execution.

A processing system, comprising:

• a bus;
• a first processing circuit configured to issue a plurality of commands via the bus;
• and
• a second processing circuit configured to receive the plurality of commands from the first processing circuit, and comprising:
• dispatch circuitry comprising:
• an insert wave memory configured to receive wave data comprising a plurality of threads from a wave feed;
• and
• a sort memory configured to store a set of state values associated with a subset of threads received at the insert wave memory based on the subset of threads being associated with a same hard key and same sort key;
• and
• shader circuitry configured to process the plurality of threads.

A streaming wave coalescer (SWC) circuit comprising:

• a memory configured to receive wave data comprising a plurality of threads from wave feed;
• a first sort bin configured to store a first set of state values associated with a first subset of threads received at the memory based on the first subset of threads corresponding to a first sort key;
• a second sort bin configured to store a second set of state values associated with a second subset of threads received at the memory based on the second subset of threads corresponding to a second sort key;
• and a third sort bin configured to store a third set of state values associated with a third subset of threads received at the memory and corresponding to sort keys having a frequency value less than a frequency threshold.