Method and apparatus for executing multiple instruction streams in a digital processor with multiple data paths

A method of processing data in a single digital processor for switching between different modes of operation, said single digital processor having a common instruction memory and first and second instruction pipelines, said first instruction pipeline comprising at least a first fetch stage, a first decoder stage and a first execute stage, said second instruction pipeline comprising a second fetch stage, a second decoder stage and a second execute stage, said method comprising the steps of:

• (1) operating in a first mode in which said first instruction pipeline is fully operational to execute instructions retrieved from said common instruction memory and said second instruction pipeline is deactivated;
• (2) activating at least a portion of said second instruction pipeline in a second mode, responsive to a first instruction being processed in said first instruction pipeline, in which said decoder stage and said execute stage of said second instruction pipeline operate upon instructions retrieved by said first fetch stage of said first instruction pipeline while said first decoder stage and said first execute stage also operate upon said instructions retrieved by said first fetch stage;
• and
• (3) deactivating said second decoder stage and said second execute stage responsive to a second instruction in said second instruction pipeline.

A single digital processor comprising:

• a first instruction pipeline comprising a first fetch stage, a first decoder stage, and a first execute stage, for processing data responsive to an instruction stream;
• a second instruction pipeline comprising a second fetch stage, a second decoder stage, and a second execute stage, for processing data responsive to an instruction stream;
• and
• control means, responsive to a first instruction in an instruction stream being processed in said first instruction pipeline, for activating said second fetch stage, said second decoder stage and said second execute stage in a first mode, whereby said first and second pipelines operate on separate instructions simultaneously,
• wherein, prior to receipt of said first instruction in an instruction stream being processed in said first instruction pipeline, said single digital processor operates in a second mode in which said first instruction pipeline is fully operational and said second instruction pipeline is deactivated except for said at least one register of said second execute stage.

A single digital processor for switching between different modes of operation, said single digital processor comprising:

• a common instruction memory for storing therein at least first and second instructions streams;
• a first instruction pipeline for executing said first instruction stream stored in said common instruction memory, said first instruction pipeline including a first fetch stage for retrieving said first instruction stream from said common instruction memory, a first decoder stage for decoding said first instruction stream retrieved by said first fetch stage, and a first execute stage for executing said first instruction stream decoded by said first decoder stage;
• at least one second instruction pipeline for executing either said first instruction stream obtained from said first instruction pipeline or said second instruction stream obtained from said common instruction memory, said second instruction pipeline including a second fetch stage for retrieving said second instruction stream from said common instruction memory, a selecting unit for selectively receiving one of said second instruction stream from said second fetch stage and said first instruction stream from said first fetch stage, a second decoder stage for decoding one of said first and second instruction streams from said selecting unit, and a second execute stage for executing said instruction stream decoded by said second decoder stage;
• a controller for activating at least a portion of said second instruction pipeline responsive to a first instruction being processed in said first instruction pipeline, so that said second instruction pipeline can execute one of said first and second instruction streams;
• and
• a common data memory, coupled to both said first and second execute stages, for storing data and processed data output from said first and second execute stages.