Chiplet-integrated machine learning accelerators

A device comprising:

• one or more machine learning accelerators;
• and
• a first chiplet memory, configured to;
• perform caching operations for a cache hierarchy of a graphics accelerator via a first portion of a cache that is present in a first chiplet that acts as an interface between the graphics accelerator and a system memory;
• in response to a request for additional directly-accessible memory for use by an accelerator of the first chiplet, reconfigure at least a first sub-portion of the first portion of the cache from being used as a cache to be used as directly-accessible memory, wherein the accelerator is configured to perform machine learning operations and to store input operands and output results into the directly-accessible memory;
• and
• explicitly request data be stored into or loaded for an address within the first sub-portion, by the accelerator.

A device, comprising:

• a first chiplet including a first chiplet memory and a first set of one or more machine learning accelerators;
• a second chiplet;
• and
• a processing core,
• wherein the first chiplet is configured to:
• perform caching operations for a cache hierarchy of a graphics accelerator of the second chiplet via a first portion of a cache that is present in the first chiplet, the first chiplet acting as an interface between the graphics accelerator and a system memory;
• and
• in response to a request for additional directly-accessible memory for use by an accelerator of the first chiplet, reconfigure at least a first sub-portion of the first portion of the cache from being used as a cache to be used as directly-accessible memory, wherein the accelerator is configured to perform machine learning operations and to store input operands and output results into the directly-accessible memory;
• and
• wherein the second chiplet is configured to explicitly request data be stored into or loaded for an address within the first sub-portion.