Sparse convolutional neural network accelerator

A processor, comprising:

• parallel processing units configured to:
• receive a first instruction including a first index vector operand and a second index vector operand;
• decode the first index vector operand to produce first coordinate sets for a first array, each first coordinate set including at least a first coordinate and a second coordinate of a position of a non-zero element in the first array;
• decode the second index vector operand to produce second coordinate sets for a second array, each second coordinate set including at least the first coordinate and the second coordinate of a position of a non-zero element in the second array;
• sum the first coordinate sets with the second coordinate sets to produce output coordinate sets;
• and
• convert the output coordinate sets into a set of linear indices.

A non-transitory, computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform steps comprising:

• receiving a first instruction including a first index vector operand and a second index vector operand;
• decoding the first index vector operand to produce first coordinate sets for a first array, each first coordinate set including at least a first coordinate and a second coordinate of a position of a non-zero element in the first array;
• decoding the second index vector operand to produce second coordinate sets for a second array, each second coordinate set including at least the first coordinate and the second coordinate of a position of a non-zero element in the second array;
• summing the first coordinate sets with the second coordinate sets to produce output coordinate sets;
• and
• converting the output coordinate sets into a set of linear indices.