G06F 9/3808
For instruction reuse
Official title: {for instruction reuse, e.g. trace cache, branch target cache}
G06F9/3808 (For instruction reuse) appears on 718 US grants and 645 published applications in this corpus.
Search patents in G06F- Granted patents
- 718
- Published applications
- 645
- Assignees
- 183
- Inventors
- 1,182
- Latest grant
- 8 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1986 | 2 | 0 |
| 1987 | 2 | 0 |
| 1988 | 2 | 0 |
| 1989 | 3 | 0 |
| 1990 | 2 | 0 |
| 1991 | 3 | 0 |
| 1992 | 3 | 0 |
| 1993 | 4 | 0 |
| 1994 | 7 | 0 |
| 1995 | 10 | 0 |
| 1996 | 9 | 0 |
| 1997 | 10 | 0 |
| 1998 | 15 | 0 |
| 1999 | 11 | 0 |
| 2000 | 17 | 0 |
| 2001 | 11 | 7 |
| 2002 | 18 | 19 |
| 2003 | 25 | 38 |
| 2004 | 26 | 29 |
| 2005 | 20 | 32 |
| 2006 | 31 | 17 |
| 2007 | 24 | 21 |
| 2008 | 20 | 28 |
| 2009 | 17 | 18 |
| 2010 | 32 | 14 |
| 2011 | 31 | 8 |
| 2012 | 11 | 25 |
| 2013 | 19 | 25 |
| 2014 | 16 | 34 |
| 2015 | 22 | 29 |
| 2016 | 41 | 35 |
| 2017 | 35 | 30 |
| 2018 | 27 | 30 |
| 2019 | 24 | 28 |
| 2020 | 25 | 32 |
| 2021 | 36 | 31 |
| 2022 | 29 | 20 |
| 2023 | 19 | 24 |
| 2024 | 20 | 23 |
| 2025 | 21 | 24 |
| 2026 | 18 | 24 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Branch target buffer run-ahead8 Sep 2026US 12,730,646 B2Microsoft Technology Licensing, LLC
- Method and apparatus for permuting streamed data elements8 Sep 2026US 12,730,758 B2Texas Instruments Incorporated
- Repeat instruction for loading and/or executing code in a claimable repeat cache a specified number of times11 Aug 2026US 12,705,055 B2Graphcore Limited
- Device for performing branch target buffer entry prefetching21 Jul 2026US 12,688,044 B2Microsoft Technology Licensing, LLC
- Flush-on-demand processor instruction trace16 Jun 2026US 12,657,029 B2Meta Platforms, Inc.
- Branch target buffer run-ahead1 Oct 2026US 2026/0299957 A1Microsoft Technology Licensing, LLC
- Fetch skipping6 Aug 2026US 2026/0228006 A1Arm Limited
- Maintenance Operations for Hierarchical Trace Cache23 Jul 2026US 2026/0211681 A1Apple Inc.
- Apparatus and method for an instruction cache miss throttler2 Jul 2026US 2026/0186785 A1
- Systems and methods for early exit from a static loop nest25 Jun 2026US 2026/0178332 A1Meta Platforms Technologies, LLC
Most cited
By later US patents
- Memory controller for a microprocessor for detecting a failure of speculation on the physical nature of a component being addressed230US 5,832,205 ATransmeta Corporation · 1998
- Method for selecting active code traces for translation in a caching dynamic translator190US 6,351,844 B1Hewlett-Packard Company · 2002
- Translated memory protection apparatus for an advanced microprocessor171US 6,199,152 B1Transmeta Corporation · 2001
- Methods for increasing instruction-level parallelism in microprocessors and digital system164US 6,988,183 B12006
- Method and apparatus for using static branch predictions hints with dynamically translated code traces to improve performance157US 6,205,545 B1Hewlett-Packard Company · 2001