Maintenance Operations for Hierarchical Trace Cache

A method, comprising:

• executing, by a computing system, control transfer instructions;
• identifying, by the computing system, traces of instructions that satisfy one or more criteria, wherein one or more of the identified traces include at least one internal taken control transfer instruction;
• storing, by the computing system, the identified traces in a trace cache hierarchy, identified traces, wherein the trace cache hierarchy includes:
• first-level trace cache storage circuitry;
• and
• second-level trace cache storage circuitry, wherein the first-level trace cache storage circuitry is closer to a processor of the computing system in the trace cache hierarchy than the second-level trace cache storage circuitry;
• and
• determining, by cache maintenance circuitry of the computing system, in response to a maintenance operation, to invalidate only a portion of valid data cached in the second-level trace cache storage circuitry, wherein the maintenance operation is one of the following maintenance operations:
• an instruction cache invalidation, a translation lookaside buffer invalidation, and a permission change.

A non-transitory computer-readable medium having instructions of a hardware description programming language stored thereon that, when processed by a computing system, program the computing system to generate a computer simulation model, wherein the model represents a hardware circuit that includes:

• processor circuitry configured to execute control transfer instructions;
• trace cache circuitry configured to:
• identify traces of instructions that satisfy one or more criteria, wherein one or more of the identified traces include at least one internal taken control transfer instruction;
• and
• store identified traces in a trace cache hierarchy, wherein the trace cache hierarchy includes:
• first-level trace cache storage circuitry;
• and
• second-level trace cache storage circuitry, wherein the first-level trace cache storage circuitry is closer to the processor circuitry in the trace cache hierarchy than the second-level trace cache storage circuitry;
• and
• cache maintenance control circuitry configured to determine, in response to a maintenance operation, whether to invalidate cached trace data in the trace cache hierarchy, wherein the cache maintenance control circuitry supports at least one of the following maintenance operations:
• an instruction cache invalidation, a translation lookaside buffer invalidation, and a permission change.