US 12,705,055 B2Granted

Repeat instruction for loading and/or executing code in a claimable repeat cache a specified number of times

AssigneeGraphcore Limited

InventorsAlan Graham Alexander, Simon Christian Knowles, Mrudula Chidambar Gore, Jonathan Ferguson

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Abstract

A processor is disclosed including: a barrel-threaded execution unit for executing concurrent threads, and a repeat cache shared between the concurrent threads. The processor's instruction set includes a repeat instruction which takes a repeat count operand. When the repeat cache is not claimed and a first repeat instruction is executed in a first thread, a portion of code is cached from the first thread into the repeat cache, the state of the repeat cache is changed to record it as claimed, and the cached code is executed a number of times. When a further repeat instruction is then executed in a further thread, the already-cached portion of code is again executed a respective number of times, each time from the repeat cache. For each of the first and further repeat instructions, the repeat count operand in the respective instruction specifies the number of times to execute the cached code.

Claims4

Dependent claims

A method of operating a processor having a barrel-threaded execution unit configured to run a plurality of concurrent threads each in a different respective one of a repeating sequence of interleaved time slots, the method comprising:

running a program comprising the plurality of concurrent threads on the processor through the execution unit, a first thread of the threads including a first instance of a repeat instruction, the repeat instruction being a machine code instruction that is defined by an opcode and that takes a repeat count operand;
executing the first instance of the repeat instruction, including, in response to the opcode of the repeat instruction:
determining that a repeat cache of the processor is not claimed;
caching a first portion of code from the first thread into the repeat cache;
recording the repeat cache as claimed;
and
executing the first portion of code a first number of times according to the repeat count operand of the first instance of the repeat instruction, taking at least one successive repetition of the first portion of code from the repeat cache;
and
resetting a state of the repeat cache as unclaimed once at least the first thread has finished executing the first portion of code the first number of times;
the method further including:
in the first thread, executing a second instance of the repeat instruction in which the repeat count operand is zero, the second instance of the repeat instruction causing the execution unit to cache a second portion of code from the first thread into the repeat cache and skip execution of the second portion of code in the first thread;
and
executing a third instance of the repeat instruction included in a second thread of said threads, including, in response to the opcode of the repeat instruction, executing the second portion of code from the repeat cache a second number of times according to the repeat count operand of the third instance of the repeat instruction, taking at least one successive repetition of the second portion of code from the repeat cache.

10 more elements

A processor comprising:

an execution unit configured to execute instances of instructions defined in an instruction set, wherein the execution unit is a barrel-threaded execution unit configured to run a plurality of concurrent threads each in a different respective one of a repeating sequence of interleaved time slots;
and
a repeat cache having an associated state recording whether or not the repeat cache is currently claimed by one of the threads;
wherein the instructions defined in the instruction set include a repeat instruction which takes a repeat count operand, the execution unit being configured so as:
in response to the opcode of the repeat instruction and in response to the repeat cache being not currently claimed according to said state and a first instance of the repeat instruction being executed in a first thread of said threads:
to cache a first portion of code from the first thread into the repeat cache, to modify said state to record the repeat cache as claimed, and to execute said first portion of code a respective number of times, taking each successive repetition of the first portion of code from the repeat cache;
wherein the processor is configured to reset said state to record the repeat cache as unclaimed again once at least the first thread has finished executing the first portion of code the respective number of times;
the execution unit further configured to, after the reset of said state:
in the first thread, execute a second instance of the repeat instruction in which the repeat count operand is zero, the second instance of the repeat instruction causing the execution unit to cache a second portion of code from the first thread into the repeat cache and skip execution of the second portion of code in the first thread;
and
execute a third instance of the repeat instruction included in a second thread of said threads, including, in response to the opcode of the repeat instruction, executing the second portion of code from the repeat cache a second number of times according to the repeat count operand of the third instance of the repeat instruction, taking at least one successive repetition of the second portion of code from the repeat cache.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/654,449Filed 11 Mar 2022 · continuation
Priority: GB 182122927 Dec 2018
Published: US 2022/0197645 A123 Jun 2022
Granted: 11 Aug 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

G06F 9/30065
To perform operations for flow control: loop control instructions; iterative instructions, e.g. LOOP, REPEAT
G06F 9/526
Program synchronisation; Mutual exclusion, e.g. by means of semaphores: mutual exclusion algorithms
G06F 9/30076
Arrangements for executing specific machine instructions: to perform miscellaneous control operations, e.g. NOP
G06F 9/3808
Instruction prefetching: for instruction reuse, e.g. trace cache, branch target cache

Family

Application16/276,895Parent of this continuation · filed 15 Feb 2019
US 2022/0197645 A1Pre-grant publication · published 23 Jun 2022
US 11,567,768 B2Parent of this continuation
US 2020/0210192 A1Published application
US 12,705,055 B2This patent

From the US filing history. Foreign family members aren’t listed.