Methods for increasing instruction-level parallelism in microprocessors and digital system
OwnerDerek Chi-Lan Wonginventor
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Abstract
Our micro-architectural method increases the performance of microprocessor and digital circuit designs by increasing the usable instruction-level parallelism during execution. The method can be applied to substantially increase the performance of processors in a broad range of instruction set architectures including CISC, RISC, and EPIC designs. Code blocks of instructions are transformed from the original instruction set architecture to be executed into a new instruction set architecture by an instruction stream transformation unit. The transformed code blocks are then cached in an instruction stream cache. The transformation process increases processor performance by substantially increasing the instruction-level parallelism available during execution.
Claims42
A processor device comprising
- an instruction stream transformation unit that transforms code blocks of instructions from an original instruction set architecture to a transformed instruction set architecture,
- a regular cache that stores instructions in said original instruction set architecture,
- an instruction stream cache that stores instructions in said transformed instruction set architecture, and
- an execute unit for executing instructions,
- wherein said instruction stream transformation unit transforms said code blocks of instructions from said original instruction set architecture to said transformed instruction set architecture,
- wherein said instruction stream cache stores said code blocks after transformation to said transformed instruction set architecture for possible future execution,
- wherein said instruction stream cache comprises means of storing and later fetching a transformed code block that spans more than one cache line in said instruction stream cache,
- wherein said instruction stream cache is addressed by some of said fetch requests from said execute unit and can potentially respond to some of said fetch requests for said code blocks after transformation without requiring cache hit information from said regular cache after said code blocks have already been transformed and stored into the instruction stream cache, and
- whereby the execution of a program code by said processor device is accelerated by transforming portions of said program code at run-time into the transformed instruction set architecture for more efficient execution and caching the transformed code within the instruction stream cache for possible repeated execution without requiring repeated transformations.
A processor device comprising an ambiguous memory conflict history table to record the history of whether previous executions of promoted ambiguous read instructions cause memory conflicts or not,
- wherein said processor device uses the history recorded in said ambiguous memory conflict history table as a predictive indicator of the likelihood of memory conflicts in subsequent executions in order to affect the scheduling order of said promoted ambiguous read instructions relative to other instructions in subsequent executions,
- whereby run-time behavior about ambiguous memory conflicts can be recorded in order to help optimize subsequent instruction scheduling.
A method of providing precise interrupts in a processor implementing instruction stream transformation comprising the steps of
- mapping an original instruction set architecture instruction to an equivalent group of one or more transformed instruction set architecture instruction(s),
- using physical registers that have not been committed to logical registers to hold results, and
- allowing the final instruction in said group to commit the physical register result(s) to logical register(s).
A method of providing precise interrupts in a processor implementing instruction stream transformation comprising the steps of
- assigning an instruction sequence number to each original instruction set architecture instruction starting from the beginning of the code block,
- marking each transformed instruction set architecture instruction with the corresponding instruction sequence number, and
- committing the results of instructions in order of the instruction sequence numbers.
Dependencies are inferred from the claim text.