Flush-on-demand processor instruction trace

A system comprising:

• a processor including:
• an instruction processing unit configured to:
• execute a plurality of machine-readable instructions of a program in accordance with a control flow of the program, and
• produce respective instruction retirement information for each of the plurality of machine-readable instructions;
• a trace encoder that is selectively enablable, wherein the trace encoder is configured to:
• receive the respective instruction retirement information, and
• encode the respective instruction retirement information in an encoded instruction trace corresponding with the control flow of the program;
• and
• a circular buffer that is configured to:
• receive the encoded instruction trace from the trace encoder;
• and
• store the encoded instruction trace;
• wherein the processor is configured to:
• enable the trace encoder;
• disable a memory interface while the trace encoder is enabled;
• receive a flush request;
• and
• enable the memory interface in response to the flush request, wherein the encoded instruction trace stored in the circular buffer is communicated over the memory interface;
• memory operationally coupled with the memory interface, the memory being configured to receive and save the encoded instruction trace received via the memory interface;
• and
• a decoder configured to, based on the plurality of machine-readable instructions of the program and the encoded instruction trace received via the memory interface, reconstruct the control flow of the program.

A method for operating a processor, the method comprising:

• receiving, by the processor, a request to enable an instruction trace mode of operation;
• in response to receiving the request to enable the instruction trace mode of operation:
• disabling a memory interface configured to communicate an instruction trace produced by a trace encoder to memory;
• executing, by an instruction processing unit of the processor, a plurality of machine-readable instructions of a program in accordance with a control flow of the program;
• producing, by the instruction processing unit for each of the plurality of machine-readable instructions, respective instruction retirement information;
• receiving, by the trace encoder, the respective instruction retirement information;
• encoding, by the trace encoder, the respective instruction retirement information in the instruction trace in correspondence with the control flow of the program;
• sending, by the trace encoder, the instruction trace to a circular buffer of the processor;
• storing, by the circular buffer, the instruction trace received from the trace encoder;
• receiving, by the processor, a request to flush the instruction trace stored in the circular buffer;
• and
• in response to receiving the request to flush the instruction trace stored in the circular buffer:
• enabling the memory interface;
• and
• communicating the instruction trace stored in the circular buffer from the circular buffer to the memory via the memory interface.