Apparatus and method for an instruction cache miss throttler

A method, comprising:

• storing instructions read from a system memory in an instruction cache;
• predicting, by a branch predictor circuit, whether one or more branch instructions will result in taken branches and responsively providing instructions pointers (IPs) corresponding to the predicted taken branches;
• storing, in a fetch queue, the IPs corresponding to the predicted taken branches, wherein the IPs are to be used to perform a lookup for corresponding instructions in the instruction cache;
• storing, in an instruction fill buffer to store, IPs of instructions from the fetch queue which missed in the instruction cache, the IPs to indicate instructions to be filled into the instruction cache from the memory subsystem;
• tracking, by tracking circuitry, a number of cachelines processed which resulted in instruction cache misses since a last predicted branch was taken;
• and
• throttling the branch predictor circuit in response to a threshold reached for the number of cachelines processed which resulted in instruction cache misses since the last predicted branch was taken.

A non-transitory machine-readable medium that stores program code that when executed by a hardware processor causes the hardware processor to perform the operations of:

• storing instructions read from a system memory in an instruction cache;
• predicting, by a branch predictor circuit, whether one or more branch instructions will result in taken branches and responsively providing instructions pointers (IPs) corresponding to the predicted taken branches;
• storing, in a fetch queue, the IPs corresponding to the predicted taken branches, wherein the IPs are to be used to perform a lookup for corresponding instructions in the instruction cache;
• storing, in an instruction fill buffer to store, IPs of instructions from the fetch queue which missed in the instruction cache, the IPs to indicate instructions to be filled into the instruction cache from the memory subsystem;
• tracking, by tracking circuitry, a number of cachelines processed which resulted in instruction cache misses since a last predicted branch was taken;
• and
• throttling the branch predictor circuit in response to a threshold reached for the number of cachelines processed which resulted in instruction cache misses since the last predicted branch was taken.