G06F 7/506
With simultaneous carry generation for, or propagation over, two or more stages
Official title: with simultaneous carry generation for, or propagation over, two or more stages
G06F7/506 (With simultaneous carry generation for, or propagation over, two or more stages) appears on 504 US grants and 244 published applications in this corpus.
Search patents in G06F- Granted patents
- 504
- Published applications
- 244
- Assignees
- 173
- Inventors
- 702
- Latest grant
- 17 Feb 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 2 | 0 |
| 1977 | 0 | 0 |
| 1978 | 3 | 0 |
| 1979 | 3 | 0 |
| 1980 | 2 | 0 |
| 1981 | 1 | 0 |
| 1982 | 2 | 0 |
| 1983 | 0 | 0 |
| 1984 | 3 | 0 |
| 1985 | 2 | 0 |
| 1986 | 5 | 0 |
| 1987 | 10 | 0 |
| 1988 | 9 | 0 |
| 1989 | 9 | 0 |
| 1990 | 10 | 0 |
| 1991 | 10 | 0 |
| 1992 | 14 | 0 |
| 1993 | 11 | 0 |
| 1994 | 13 | 0 |
| 1995 | 10 | 0 |
| 1996 | 20 | 0 |
| 1997 | 13 | 0 |
| 1998 | 14 | 0 |
| 1999 | 24 | 0 |
| 2000 | 17 | 0 |
| 2001 | 32 | 4 |
| 2002 | 21 | 9 |
| 2003 | 22 | 23 |
| 2004 | 17 | 21 |
| 2005 | 12 | 19 |
| 2006 | 18 | 11 |
| 2007 | 16 | 10 |
| 2008 | 15 | 10 |
| 2009 | 8 | 12 |
| 2010 | 14 | 3 |
| 2011 | 8 | 8 |
| 2012 | 5 | 3 |
| 2013 | 9 | 4 |
| 2014 | 5 | 8 |
| 2015 | 5 | 5 |
| 2016 | 8 | 16 |
| 2017 | 16 | 3 |
| 2018 | 9 | 2 |
| 2019 | 6 | 20 |
| 2020 | 13 | 7 |
| 2021 | 7 | 9 |
| 2022 | 6 | 6 |
| 2023 | 10 | 14 |
| 2024 | 6 | 6 |
| 2025 | 7 | 9 |
| 2026 | 2 | 2 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Asynchronous full-adder with majority or minority gates to generate an enable or an acknowledgement17 Feb 2026US 12,554,462 B1Kepler Computing Inc.
- Asynchronous full-adder with majority or minority gates to generate sum true output13 Jan 2026US 12,524,205 B1Kepler Computing Inc.
- Asynchronous carry-ripple adder with majority or minority gates25 Nov 2025US 12,481,481 B2Kepler Computing Inc.
- Asynchronous full-adder with majority or minority gates to generate carry-out true output9 Sep 2025US 12,411,657 B1Kepler Computing Inc.
- Asynchronous full-adder with majority or minority gates to generate carry-out false output2 Sep 2025US 12,405,768 B1Kepler Computing Inc.
- High-speed selective carry propagate adder13 Aug 2026US 2026/0236721 A1Indian Institute of Technology Madras (Iit Madras)
- Ripple carry full adder circuit14 May 2026US 2026/0133759 A1Samsung Electronics Co., Ltd.
- Signed extension carry-look-ahead for accumulator with bit width difference27 Nov 2025US 2025/0362872 A1Taiwan Semiconductor Manufacturing Company.Ltd
- New low power adder tree structure6 Nov 2025US 2025/0342007 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Analog computation of shift and add for dot product engines30 Oct 2025US 2025/0335154 A1
Most cited
By later US patents
- Method and apparatus for designing circuits for wave pipelining258US 5,796,624 AThe Research Foundation of State University of New York · 1998
- Adder/substractor for variable length numbers188US 4,707,800 ARaytheon Company · 1987
- Fast carry structure with synchronous input159US 5,546,018 AXilinx, Inc. · 1996
- Interconnection and input/output resources for programmable logic integrated circuit devices147US 6,407,576 B1Altera Corporation · 2002
- Logic structure and circuit for fast carry138US 5,267,187 A1993