G06F 7/505
In bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
Official title: in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
G06F7/505 (In bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination) appears on 1,017 US grants and 489 published applications in this corpus.
Search patents in G06F- Granted patents
- 1,017
- Published applications
- 489
- Assignees
- 298
- Inventors
- 1,497
- Latest grant
- 17 Feb 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 9 | 0 |
| 1977 | 2 | 0 |
| 1978 | 5 | 0 |
| 1979 | 5 | 0 |
| 1980 | 4 | 0 |
| 1981 | 4 | 0 |
| 1982 | 5 | 0 |
| 1983 | 3 | 0 |
| 1984 | 5 | 0 |
| 1985 | 11 | 0 |
| 1986 | 9 | 0 |
| 1987 | 15 | 0 |
| 1988 | 12 | 0 |
| 1989 | 26 | 0 |
| 1990 | 27 | 0 |
| 1991 | 18 | 0 |
| 1992 | 26 | 0 |
| 1993 | 23 | 0 |
| 1994 | 30 | 0 |
| 1995 | 21 | 0 |
| 1996 | 36 | 0 |
| 1997 | 36 | 0 |
| 1998 | 28 | 0 |
| 1999 | 48 | 0 |
| 2000 | 37 | 0 |
| 2001 | 49 | 9 |
| 2002 | 38 | 20 |
| 2003 | 38 | 40 |
| 2004 | 32 | 32 |
| 2005 | 19 | 29 |
| 2006 | 32 | 27 |
| 2007 | 24 | 16 |
| 2008 | 22 | 14 |
| 2009 | 23 | 19 |
| 2010 | 20 | 10 |
| 2011 | 11 | 16 |
| 2012 | 13 | 8 |
| 2013 | 23 | 10 |
| 2014 | 13 | 13 |
| 2015 | 8 | 8 |
| 2016 | 16 | 22 |
| 2017 | 23 | 6 |
| 2018 | 15 | 12 |
| 2019 | 18 | 41 |
| 2020 | 27 | 29 |
| 2021 | 18 | 22 |
| 2022 | 23 | 21 |
| 2023 | 30 | 29 |
| 2024 | 15 | 15 |
| 2025 | 19 | 16 |
| 2026 | 3 | 5 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
- G06F 7/506With simultaneous carry generation for, or propagation over, two or more stages504
- G06F 7/509For multiple operands241
- G06F 7/5055In which one operand is a constant, i.e. incrementers or decrementers84
- G06F 7/5057Using table look-up54
- G06F 7/5052Using carry completion detection, either over all stages or at sample stages29
Recent patents
- Asynchronous full-adder with majority or minority gates to generate an enable or an acknowledgement17 Feb 2026US 12,554,462 B1Kepler Computing Inc.
- Apparatus and method for performing accumulation operations27 Jan 2026US 12,535,991 B2Arm Limited
- Asynchronous full-adder with majority or minority gates to generate sum true output13 Jan 2026US 12,524,205 B1Kepler Computing Inc.
- Asynchronous carry-ripple adder with majority or minority gates25 Nov 2025US 12,481,481 B2Kepler Computing Inc.
- Computing device, computing apparatus and method of warp accumulation18 Nov 2025US 12,475,190 B2Shanghai Biren Technology Co., Ltd
- High-speed selective carry propagate adder13 Aug 2026US 2026/0236721 A1Indian Institute of Technology Madras (Iit Madras)
- Multiple-Input Floating-Point Processing With Mantissa Bit Extension11 Jun 2026US 2026/0161355 A1Imagination Technologies Limited
- Ripple carry full adder circuit14 May 2026US 2026/0133759 A1Samsung Electronics Co., Ltd.
- Accumulation Systems and Methods30 Apr 2026US 2026/0119124 A2VeriSilicon Holdings Co., Ltd.
- Method and apparatus for generating hardware interface signal, and electronic device5 Feb 2026US 2026/0037466 A1Suzhou Metabrain Intelligent Technology Co., Ltd.
Most cited
By later US patents
- Method and apparatus for designing circuits for wave pipelining258US 5,796,624 AThe Research Foundation of State University of New York · 1998
- Devices and methods with programmable logic and digital signal processing regions256US 6,538,470 B1Altera Corporation · 2003
- Adder/substractor for variable length numbers188US 4,707,800 ARaytheon Company · 1987
- Fast carry structure with synchronous input159US 5,546,018 AXilinx, Inc. · 1996
- Interconnection and input/output resources for programmable logic integrated circuit devices147US 6,407,576 B1Altera Corporation · 2002