G06F 7/5052
Using carry completion detection, either over all stages or at sample stages
Official title: {using carry completion detection, either over all stages or at sample stages only}
G06F7/5052 (Using carry completion detection, either over all stages or at sample stages) appears on 29 US grants and 4 published applications in this corpus.
Search patents in G06F- Granted patents
- 29
- Published applications
- 4
- Assignees
- 15
- Inventors
- 35
- Latest grant
- 15 Oct 2024
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 0 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 1 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 1 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 1 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 1 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 5 | 0 |
| 1998 | 4 | 0 |
| 1999 | 1 | 0 |
| 2000 | 4 | 0 |
| 2001 | 1 | 0 |
| 2002 | 3 | 0 |
| 2003 | 1 | 0 |
| 2004 | 0 | 0 |
| 2005 | 3 | 2 |
| 2006 | 0 | 0 |
| 2007 | 0 | 0 |
| 2008 | 0 | 0 |
| 2009 | 0 | 0 |
| 2010 | 0 | 0 |
| 2011 | 0 | 0 |
| 2012 | 0 | 0 |
| 2013 | 0 | 0 |
| 2014 | 0 | 0 |
| 2015 | 0 | 0 |
| 2016 | 0 | 0 |
| 2017 | 0 | 0 |
| 2018 | 0 | 0 |
| 2019 | 0 | 0 |
| 2020 | 0 | 0 |
| 2021 | 0 | 1 |
| 2022 | 0 | 0 |
| 2023 | 1 | 1 |
| 2024 | 1 | 0 |
By publication year. Applications have been published since 2001.
Recent patents
- In-memory bit-serial addition system15 Oct 2024US 12,118,328 B2Purdue Research Foundation
- In-memory bit-serial addition system6 Jun 2023US 11,669,302 B2Purdue Research Foundation
- Calculating unit and method for subtracting29 Nov 2005US 6,970,899 B2Infineon Technologies AG
- Calculating unit and method for adding15 Nov 2005US 6,965,910 B2Infineon Technologies AG
- Null convention threshold gate31 May 2005US 6,900,658 B1Theseus Logic, Inc.
- In-memory bit-serial addition system28 Sep 2023US 2023/0305804 A1Purdue Research Foundation
- In-memory bit-serial addition system22 Apr 2021US 2021/0117156 A1Purdue Research Foundation
- Calculating unit and method for subtracting5 May 2005US 2005/0097156 A1Infineon Technologies AG
- Calculating unit and method for adding5 May 2005US 2005/0097157 A1Infineon Technologies AG
Most cited
By later US patents
- Encryption processor with shared memory interconnect123US 6,434,699 B1Mosaid Technologies Incorporated · 2002
- Encryption processor with shared memory interconnect93US 6,088,800 AMosaid Technologies Incorporated · 2000
- Asynchronous processors48US 5,752,070 ACalifornia Institute of Technology · 1998
- Null convention logic system35US 5,305,463 ATheseus Research, Inc. · 1994
- Null convention bus28US 5,796,962 ATheeus Logic · 1998