Encryption processor with shared memory interconnect
AssigneeMosaid Technologies Incorporated
InventorsDavid E. Jones, Cormac M. O'Connell
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Abstract
An encryption chip is programmable to process a variety of secret key and public key encryption algorithms. The chip includes a pipeline of processing elements, each of which can process a round within a secret key algorithm. Data is transferred between the processing elements through dual port memories. A central processing unit allows for processing of very wide data words from global memory in single cycle operations. An adder circuit is simplified by using plural relatively small adder circuits with sums and carries looped back in plural cycles. Multiplier circuitry can be shared between the processing elements and the central processor by adapting the smaller processing element multipliers for concatenation as a very wide central processor multiplier.
Claims52
An electronic encryption device comprising, on a single chip, an array of processing elements, each processing element comprising:
- an instruction memory for storing a round of an encryption algorithm, the round comprising a sequence of instructions;
- a processor for implementing the round from the instruction memory;
- data storage for storing encryption data operands and encrypted data resulting from implementing the round;
- processing elements of the array each implementing one of the rounds and transferring results to successive processing elements such that the array of processing elements implements successive rounds of the encryption algorithm in a processing element pipeline.
An electronic encryption device comprising, on a single chip, a linear array of processing elements, each processing element comprising:
- an instruction memory for storing code required to implement at least a round of an encryption algorithm;
- a processor for processing the round from the instruction memory;
- local data memory;
- shared data storage between two adjacent processing elements;
- processing elements of the linear array each implementing one of the rounds and transferring results to successive processing elements such that the linear array of processing elements processes successive rounds of the encryption algorithm in a processing element pipeline.
An encryption data processing system comprising a linear array of processing elements, each processing element comprising:
- an instruction memory;
- a processor for processing instructions from the instruction memory;
- data memory;
- data memories of the processing elements of the linear array comprising dual port memories shared between adjacent processing elements for transfer of data between adjacent processing elements of the linear array.
A multiplier circuit comprising:
- a plurality of multiplier segments, each receiving operand words of a first length;
- and
- input selectors which select a first set of inputs when the multiplier segments operate as individual multipliers and a second set of inputs to concatenate the multiplier segments as a wider multiplier operating on operands of a second word length.
An adder comprising:
- plural adder segments, each having a carry output and a sum output, each of the adder segments processing a segment of each of two operands;
- carry selectors to select the carry outputs as carry input to successive adder segments for successive clock cycles so long as any carry results in an adder cycle;
- and
- operand selectors to select each carry output as an operand input to the same adder segment for successive clock cycles so long as any carry results in an adder cycle.
An electronic encryption device comprising, on a single chip:
- a linear array of processing elements, each comprising an instruction store, data storage, and a processor which processes a sequence of instructions from the instruction store to operate on data words of a first length, the data storage of the processing elements including dual port memories shared between adjacent processing elements for transfer of data between adjacent processing elements of the array, the processing elements of the linear array having stored in their instruction stores respective rounds of an encryption algorithm and transferring results of the rounds to successive processing elements such that the linear array of processing elements processes successive rounds of the encryption algorithm in a processing element pipeline;
- a global random access memory;
- a global bus to which data is transferred between the global random access memory and the processing element data memories;
- and
- a public key encryption processor operating on data words of a second length at least an order of magnitude longer than the first length, the public key processor accessing global random access memory in word lengths of the second length.
An electronic encryption device comprising, on a single chip, an array of processing elements, each processing element comprising:
- instruction memory means for storing a round of an encryption algorithm;
- processor means for implementing the round from the instruction memory;
- and
- data storage means for storing encryption data operands and encrypted data resulting from implementing the round.
A method of encryption comprising:
- in an electronic circuit on a single chip, receiving data to be encrypted;
- applying the data to a pipeline of data processing elements on the chip, each processing element processing an encryption round and transferring results to successive processing elements such that the processing elements implement successive rounds of the encryption algorithm in a processing element pipeline.
Dependencies are inferred from the claim text.