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US 5,796,962 AGranted
Null convention bus
AssigneeTheeus Logic
InventorsKarl M. Fant, Larry L. Kinney
Life of this patent
Estimating the term…
Abstract
A NULL convention logic bus includes: a plurality of bus transmission lines; a plurality of NULL convention transmitter ports; and a plurality of NULL convention receiver ports. Each NULL convention transmitter port propagates alternating wavefronts of data an NULL across the bus transmission lines to a NULL convention receiver port. A pipeline bus includes NULL convention storage registers at the transmitter ports. A FIFO pipeline bus includes NULL convention storage registers at the receiver ports.
Claims50
A logic bus comprising:
- a plurality of bus transmission lines, each transmission line having at least a first state representative of the presence of asserted data, and a NULL state having no data significance;
- a plurality of transmitter ports;
- and
- a plurality of receiver ports;
- wherein at least one transmitter port asynchronously propagates alternating wavefronts of data and NULL across the bus transmission lines to at least an addressable one of said receiver ports.
2 more elements
A pipeline logic bus comprising:
- a plurality of bus transmission lines, each transmission line having at least a first state representative of the presence of asserted data, and a NULL state having no data significance;
- a plurality of transmitter ports;
- and
- a plurality of receiver ports, a first receiver port including an asynchronous storage register;
- wherein at least one transmitter port asynchronously propagates alternating wavefronts of data and NULL across the bus transmission lines to at least one receiver port.
2 more elements
A buffered logic bus comprising:
- a plurality of bus transmission lines, each transmission line having at least a first state representative of the presence of asserted data, and a NULL state having no data significance;
- a plurality of transmitter ports;
- and
- a plurality of receiver ports, a first receiver port including first and second receiver asynchronous storage registers;
- wherein at least one transmitter port asynchronously propagates alternating wavefronts of data an NULL across the bus transmission lines to at least one receiver port.
2 more elements
Dependencies are inferred from the claim text.