In-memory bit-serial addition system
AssigneePurdue Research Foundation
InventorsMustafa Ali, Akhilesh Jaiswal, Kaushik Roy
Life of this patent
Estimating the term…
Abstract
An in-memory vector addition method for a dynamic random access memory (DRAM) is disclosed which includes consecutively transposing two numbers across a plurality of rows of the DRAM, each number transposed across a fixed number of rows associated with a corresponding number of bits, assigning a scratch-pad including two consecutive bits for each bit of each number being added, two consecutive bits for carry-in (Cin), and two consecutive bits for carry-out-bar (Cout), assigning a plurality of bits in a transposed orientation to hold results as a sum of the two numbers, for each bit position of the two numbers: computing the associated sum of the bit position; and placing the computed sum in the associated bit of the sum.
Claims20
An in-memory vector addition method for a dynamic random access memory (DRAM), comprising:
- consecutively transposing two numbers across a plurality of rows of the DRAM, each number transposed across a fixed number of rows associated with a corresponding number of bits;
- assigning a plurality of compute rows in the same transpose manner including
- two consecutive bits for each bit of each number being added,
- two consecutive bits for carry-in (Cin), and
- two consecutive bits for carry-out-bar (Cout);
- assigning a plurality of bits in the same transpose manner to hold results as a sum of the two numbers;
- for each bit position of the two numbers:
- determining associated sum(S) of the associated bit positions of the two numbers;
- and
- placing the determined associated sum in the associated bit of the sum,
- wherein the determination of the associated sum is based on determining a Cout and Cout and recording the determined Cout and Cout in associated bit positions of the plurality of compute rows, and
- wherein Cout associated with determination of the associated sum of one bit is used as Cin for determination of the associated sum of a next bit.
A dynamic random access memory (DRAM) capable of in-memory vector addition, comprising:
- a DRAM comprising a data addition area having a plurality of rows, each row including a plurality of columns;
- a first subset of the plurality of rows of the data addition area assigned to hold consecutively transposed two numbers across a first column, each number transposed across a fixed number of rows of the first subset associated with a corresponding number of bits;
- a second subset of the plurality of rows of the data addition area assigned as summation result rows across the first column associated with a sum of the two numbers;
- a third subset of the plurality of rows of the data addition rows area assigned as a plurality of compute rows across the first column including two consecutive bits for each bit of each number being added, two consecutive bits for carry-in (Cin), and two consecutive bits for carry-out-bar (Cout);
- and
- a memory controller configured to:
- for each bit position of the two numbers:
- determine associated sum(S) of the associated bit positions of the two numbers;
- and
- place the determined associated sum in the associated bit of the sum,
- wherein the determination of the associated sum is based on determining a Cout and Cout and recording the determined Cout and Cout in associated bit positions of the plurality of compute rows, and
- wherein Cout associated with determination of the associated sum of one bit is used as Cin for determination of the associated sum of a next bit.
Dependencies are inferred from the claim text.