In-memory bit-serial addition system

An in-memory vector addition method for a dynamic random access memory (DRAM), comprising:

• consecutively transposing two numbers across a plurality of rows of the DRAM, each number transposed across a fixed number of rows associated with a corresponding number of bits;
• assigning a plurality of compute rows in the same transpose manner including
• two consecutive bits for each bit of each number being added,
• two consecutive bits for carry-in (Cin), and
• two consecutive bits for carry-out-bar (Cout);
• assigning a plurality of bits in the same transpose manner to hold results as a sum of the two numbers;
• for each bit position of the two numbers:
• determining associated sum (S) of the associated bit positions of the two numbers;
• and
• placing the determined associated sum in the associated bit of the sum
• wherein the determination of the associated sum is based on determining a Cout and Cout and recording the determined Cout and Cout in associated bit positions of the plurality of compute rows utilizing dual contact cells for Coutassociated bit positions each with two associated access transistors where one of the two associated access transistors is controlled by a first control line and the second of the two associated access transistors is controlled by a second control line opposite the first control line, and
• wherein Cout associated with determination of the associated sum of one bit is used as Cin for determination of the associated sum of a next bit.