Asynchronous full-adder with majority or minority gates to generate an enable or an acknowledgement

An apparatus comprising:

• a first data channel comprising two first inputs and a first acknowledgement output;
• a second data channel comprising two second inputs and a second acknowledgement output;
• a third data channel comprising two carry inputs and a third acknowledgement output;
• a fourth data channel comprising two carry outputs and a third acknowledgement input;
• a fifth data channel comprising two sum outputs and a fourth acknowledgement input;
• and
• a full-adder coupled to the first data channel, the second data channel, the third data channel, the fourth data channel, and the fifth data channel, wherein the full-adder comprises majority and/or minority gates some of which receive the two first inputs, the two second inputs, the two carry inputs, the third acknowledgement input, and the fourth acknowledgement input, and generate controls to control gates of transistors, wherein the transistors are coupled to generate the two carry outputs, the two sum outputs, the first acknowledgement output, the second acknowledgement output, and the third acknowledgement output, and wherein the full-adder comprises a circuitry to generate the first acknowledgement output, the second acknowledgement output, and the third acknowledgement output.