G06F 7/5055
In which one operand is a constant, i.e. incrementers or decrementers
Official title: {in which one operand is a constant, i.e. incrementers or decrementers}
G06F7/5055 (In which one operand is a constant, i.e. incrementers or decrementers) appears on 84 US grants and 33 published applications in this corpus.
Search patents in G06F- Granted patents
- 84
- Published applications
- 33
- Assignees
- 52
- Inventors
- 146
- Latest grant
- 4 Apr 2023
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 1 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 1 | 0 |
| 1981 | 1 | 0 |
| 1982 | 0 | 0 |
| 1983 | 2 | 0 |
| 1984 | 1 | 0 |
| 1985 | 0 | 0 |
| 1986 | 2 | 0 |
| 1987 | 4 | 0 |
| 1988 | 0 | 0 |
| 1989 | 2 | 0 |
| 1990 | 2 | 0 |
| 1991 | 4 | 0 |
| 1992 | 3 | 0 |
| 1993 | 1 | 0 |
| 1994 | 3 | 0 |
| 1995 | 4 | 0 |
| 1996 | 4 | 0 |
| 1997 | 4 | 0 |
| 1998 | 1 | 0 |
| 1999 | 2 | 0 |
| 2000 | 2 | 0 |
| 2001 | 1 | 0 |
| 2002 | 4 | 2 |
| 2003 | 3 | 7 |
| 2004 | 9 | 6 |
| 2005 | 2 | 3 |
| 2006 | 2 | 3 |
| 2007 | 3 | 1 |
| 2008 | 4 | 0 |
| 2009 | 3 | 2 |
| 2010 | 1 | 0 |
| 2011 | 0 | 0 |
| 2012 | 0 | 2 |
| 2013 | 2 | 2 |
| 2014 | 1 | 1 |
| 2015 | 0 | 0 |
| 2016 | 2 | 1 |
| 2017 | 1 | 0 |
| 2018 | 0 | 0 |
| 2019 | 0 | 1 |
| 2020 | 0 | 1 |
| 2021 | 0 | 0 |
| 2022 | 0 | 0 |
| 2023 | 1 | 0 |
| 2024 | 0 | 0 |
| 2025 | 0 | 0 |
| 2026 | 0 | 1 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Parallel hybrid adder4 Apr 2023US 11,620,106 B1The United States of America as represented by the Secretary of the Navy
- Increment/decrement apparatus and method10 Oct 2017US 9,785,405 B2Huawei Technologies Co., Ltd.
- Three-term predictive adder and/or subtracter20 Sep 2016US 9,448,767 B2Texas Instruments Incorporated
- Expanded scope incrementer10 May 2016US 9,335,968 B2International Business Machines Corporation
- Three-term predictive adder and/or subtracter29 Apr 2014US 8,713,086 B2Texas Instruments Incorporated
- Method and apparatus for generating hardware interface signal, and electronic device5 Feb 2026US 2026/0037466 A1Suzhou Metabrain Intelligent Technology Co., Ltd.
- Higher-order data sketching for ad-hoc query estimation13 Aug 2020US 2020/0257684 A1Red Hat, Inc.
- Secure storage of monotonic odo value inside a secure hardware elements update counter20 Jun 2019US 2019/0190899 A1
- Increment/Decrement Apparatus and Method1 Dec 2016US 2016/0350076 A1Huawei Technologies Co., Ltd.
- Three-Term Predictive Adder and/or Subtracter26 Jun 2014US 2014/0181165 A1Texas Instruments Incorporated
Most cited
By later US patents
- Loadable up-down counter with asynchronous reset44US 6,157,209 AXilinx, Inc. · 2000
- Method and system for compiling circuit designs44US 6,711,717 B2California Institute of Technology · 2004
- Pointer for use with a buffer and method of operation39US 5,450,560 AMotorola, Inc. · 1995
- Absolute value calculating circuit having a single adder33US 4,953,115 ANEC Corporation · 1990
- Conditional carry techniques for digital processors27US 4,623,982 AHewlett-Packard Company · 1986