Method and system for compiling circuit designs

Abstract

The present invention is a programming language method called Pipeline Language 1 (PL1) and its associated compiler system for generating logical circuit designs. The semantics allow the implementation to add more slack than exists in the specification, aiding the design of slack-elastic systems. In PL1, the value probe and peek are the most basic operations: receiving a value is done by first using the peek, and then acknowledging it as a separate action. Another embodiment is a PL1 compiler comprised of a technology-independent front-end module and a technology-dependent back-end module. It parses the input, converts it into BDD expressions, checks determinism conditions, generates BDD expressions for assignments and sends and converts the BDD expressions to unary representation. The back-end compiler module is technology-dependent, meaning that different back-end modules generate different circuit design types (e.g. QDI and STAPL). All back-end module embodiments perform logic simplification on input programs.

Dependencies are inferred from the claim text.