Three-Term Predictive Adder and/or Subtracter

A predictive adder forming the sum of two inputs and subtract a 2k constant, comprising:

• a full adder receiving a first operand and a second operand operable to produce a sum of the first and second operand and to generate a carry output in response to the addition of the first and second operands;
• and
• at least one of a consecutive ones predictor and a consecutive zeros predictor, wherein the consecutive ones predictor is arranged to evaluate the first and second operands to generate an indication of a ripple portion of bits in a potential sum of the first and second operands that are predicted to be toggled by incrementing the potential sum of the first and second operands at a bit position determined by k, where k determines a one-bit constant of the form 2k, and that is arranged to produce the sum of the first and second operands and the one-bit constant in response to the indication of the ripple portion of bits in the potential sum of the first and second operands and the carry output generated by the full adder, and wherein the consecutive zeros predictor is arranged to evaluate the first and second operands to generate an indication of a ripple portion of bits in the potential sum of the first and second operands that are predicted to be toggled by incrementing the potential sum of the first and second operands at a bit position determined by k, where k determines a one-bit constant of the form 2k, and that is arranged to produce the sum of the first and second operands with the one-bit constant subtracted therefrom in response to the indication of the ripple portion of bits in the potential sum of the first and second operands and the carry output generated by the full adder.

A predictive adder comprising:

• an adder having
• an adder carry tree having a first input receiving a first operand and a second input receiving a second operand operable to generate all carries of Carry (A, B) for respective bit positions a sum of said first operand and said second operand on an output,
• a first exclusive OR gate having a first input receiving said first operand and a second input receiving said second operand operable to generate exclusive ORs of corresponding bits of said first operand and said second operand on an output,
• a first inverter having an input connected to said output of said exclusive OR gate operable to generate an inverse of each bit of said output of said exclusive OR gate on an output, and
• a first multiplexer having a first input connected to output of said first exclusive OR gate, a second input connected to said output of said first inverter and a control input connected to said output of said adder carry tree operable to generate a sum output selecting a bit of said output of said first exclusive OR gate or a corresponding bit of said output of said first inverter dependent upon the digital state of a corresponding bit of said carry;
• an incrementer including
• a consecutive ones predictor/shifter having a first input receiving said first operand, a second input receiving said second operand and a third input receiving a constant having the form 2k, where k is an integer, operable to detect a number of consecutive 1's more significant than the k-th bit, invert each of said detected consecutive 1's and a next more significant bit, generating an exclusive OR with a partial sum of said first operand and said second operand and on an output,
• a second exclusive OR gate having a first input receiving said output of said first exclusive OR gate and a second input receiving said output of said consecutive ones predictor/shifter operable to generate exclusive ORs of corresponding bits of said output of said first exclusive OR gate and said output of said consecutive ones predictor/shifter on an output,
• a second inverter having an input connected to said output of said second exclusive OR gate operable to generate an inverse of each bit of said output of said second exclusive OR gate on an output, and
• a second multiplexer having a first input connected to output of said second exclusive OR gate, a second input connected to said output of said second inverter and a control input connected to said output of said adder carry tree operable to generate a sum output selecting a bit of said output of said second exclusive OR gate or a corresponding bit of said output of said second inverter dependent upon the digital state of a corresponding bit of said carry;
• and
• a decrementer including
• a consecutive zeros predictor/shifter having a first input receiving said first operand, a second input receiving said second operand and a third input receiving a constant having the form 2k, where k is an integer, operable to detect a number of consecutive 0's more significant than the k-th bit, invert each of said detected consecutive 0's and a next more significant bit, generating an exclusive OR with a partial sum of said first operand and said second operand and on an output,
• a consecutive zeros predictor/shifter having a first input receiving said first operand, a second input receiving said second operand and a third input receiving a constant having the form −2k, where k is an integer, operable to detect
• a number of consecutive 1's
• a third exclusive OR gate having a first input receiving said output of said first exclusive OR gate and a second input receiving said output of said consecutive zeros predictor/shifter operable to generate exclusive ORs of corresponding bits of said output of said first exclusive OR gate and said output of said consecutive ones predictor/shifter on an output,
• a third inverter having an input connected to said output of said third exclusive OR gate operable to generate an inverse of each bit of said output of said third exclusive OR gate on an output, and
• a third multiplexer having a first input connected to output of said third exclusive OR gate, a second input connected to said output of said third inverter and a control input connected to said output of said adder carry tree operable to generate a sum output selecting a bit of said output of said third exclusive OR gate or a corresponding bit of said output of said third inverter dependent upon the digital state of a corresponding bit of said carry.

A predictive adder comprising:

• an adder having
• an adder carry tree having a first input receiving a first operand and a second input receiving a second operand operable to generate all carries of Carry (A, B) for respective bit positions a sum of said first operand and said second operand on an output,
• a first exclusive OR gate having a first input receiving said first operand and a second input receiving said second operand operable to generate exclusive ORs of corresponding bits of said first operand and said second operand on an output,
• a first inverter having an input connected to said output of said exclusive OR gate operable to generate an inverse of each bit of said output of said exclusive OR gate on an output, and
• a first multiplexer having a first input connected to output of said first exclusive OR gate, a second input connected to said output of said first inverter and a control input connected to said output of said adder carry tree operable to generate a sum output selecting a bit of said output of said first exclusive OR gate or a corresponding bit of said output of said first inverter dependent upon the digital state of a corresponding bit of said carry;
• and
• an incrementer including
• a consecutive ones predictor/shifter having a first input receiving said first operand, a second input receiving said second operand and a third input receiving a constant having the form 2k, where k is an integer, operable to detect a number of consecutive 1's more significant than the k-th bit, invert each of said detected consecutive 1's and a next more significant bit, generating an exclusive OR with a partial sum of said first operand and said second operand and on an output,
• a second exclusive OR gate having a first input receiving said output of said first exclusive OR gate and a second input receiving said output of said consecutive ones predictor/shifter operable to generate exclusive ORs of corresponding bits of said output of said first exclusive OR gate and said output of said consecutive ones predictor/shifter on an output,
• a second inverter having an input connected to said output of said second exclusive OR gate operable to generate an inverse of each bit of said output of said second exclusive OR gate on an output, and
• a second multiplexer having a first input connected to output of said second exclusive OR gate, a second input connected to said output of said second inverter and a control input connected to said output of said adder carry tree operable to generate a sum output selecting a bit of said output of said second exclusive OR gate or a corresponding bit of said output of said second inverter dependent upon the digital state of a corresponding bit of said carry.

A predictive adder comprising:

• an adder having
• an adder carry tree having a first input receiving a first operand and a second input receiving a second operand operable to generate all carries of Carry (A, B) for respective bit positions a sum of said first operand and said second operand on an output,
• a first exclusive OR gate having a first input receiving said first operand and a second input receiving said second operand operable to generate exclusive ORs of corresponding bits of said first operand and said second operand on an output,
• a first inverter having an input connected to said output of said exclusive OR gate operable to generate an inverse of each bit of said output of said exclusive OR gate on an output, and
• a first multiplexer having a first input connected to output of said first exclusive OR gate, a second input connected to said output of said first inverter and a control input connected to said output of said adder carry tree operable to generate a sum output selecting a bit of said output of said first exclusive OR gate or a corresponding bit of said output of said first inverter dependent upon the digital state of a corresponding bit of said carry;
• and
• a decrementer including
• a consecutive zeros predictor/shifter having a first input receiving said first operand, a second input receiving said second operand and a third input receiving a constant having the form 2k, where k is an integer, operable to detect a number of consecutive 0's more significant than the k-th bit, invert each of said detected consecutive 0's and a next more significant bit, generating an exclusive OR with a partial sum of said first operand and said second operand and on an output,
• a third exclusive OR gate having a first input receiving said output of said first exclusive OR gate and a second input receiving said output of said consecutive zeros predictor/shifter operable to generate exclusive ORs of corresponding bits of said output of said first exclusive OR gate and said output of said consecutive ones predictor/shifter on an output,
• a third inverter having an input connected to said output of said third exclusive OR gate operable to generate an inverse of each bit of said output of said third exclusive OR gate on an output, and
• a third multiplexer having a first input connected to output of said third exclusive OR gate, a second input connected to said output of said third inverter and a control input connected to said output of said adder carry tree operable to generate a sum output selecting a bit of said output of said third exclusive OR gate or a corresponding bit of said output of said third inverter dependent upon the digital state of a corresponding bit of said carry.