US 5,450,560 AGranted

Pointer for use with a buffer and method of operation

AssigneeMotorola, Inc.

InventorsJeffrey T. Bridges, Lawrence W. Osborne

Life of this patent

Estimating the term…

Loading patent…

Abstract

A pointer (86) has generate circuitry (90), propagate circuitry (90), carry circuitry (90) and detector circuitry (92). The pointer is for use with a buffer to designate one of a plurality of entries of the buffer. The generate circuitry receives a first and a second data word and generates a plurality of local generate functions. One bit of the first data word, second data word, and one of the local generate functions each corresponds to one of the entries of the buffer. Each data bit of the first data word is representative of the eligibility of the pointer to designate an entry. The second data word is representative of the pointer location at a previous time. The propagate circuitry receives the first and second data words and generates a plurality of local propagate functions. Each local propagate function corresponds to one of the entries of the buffer. The carry circuitry is coupled to the generate circuitry and to the propagate circuitry and generates a plurality of carry bits. Each carry bit corresponds to one of the entries of the buffer. The detector circuitry is coupled to the carry circuitry and detects a predetermined pattern within the plurality of carry bits. The output of the detector circuitry is coupled to the second data word. The pointer may be designed in modules. A modular design procedure makes the pointer easily adapted for applications with different size buffers while maintaining the pointer's high speed performance.

Claims15

Dependent claims

A pointer for use with a buffer, the pointer operable to designate one of a plurality of entries of the buffer responsive to input data and responsive to a prior designated entry, the pointer comprising:

generate circuitry for receiving a first and a second data word, said first and second data words each comprising a plurality of data bits, one bit of each first and second data word corresponding to one of the entries of the buffer, a logic state of each data bit of the first data word representative of the eligibility of said pointer to designate an entry, said second data word representative of the pointer location at a previous time, said generate circuitry generating a plurality of local generate functions, each local generate function corresponding to one of the entries of the buffer;
propagate circuitry for receiving said first and second data words, said propagate circuitry generating a plurality of local propagate functions, each local propagate function corresponding to one of said entries of said buffer;
carry circuitry coupled to said generate circuitry and to said propagate circuitry, said carry circuitry generating a plurality of carry bits, a first one of said plurality of carry bits being a function of an input carry bit, one of said plurality of local generate functions, and one of said plurality of local propagate functions, a second one of said plurality of carry bits being a function of another of said plurality of carry bits, another of said plurality of local generate functions, and another of said plurality of local propagate functions, each carry bit corresponding to one of the entries of said buffer;
and
detector circuitry coupled to said carry circuitry, said carry circuitry for receiving said plurality of carry bits, said detector circuitry detecting a predetermined pattern within said plurality of carry bits, an output of said detector circuitry coupled to said second data word, a position of said predetermined pattern identifying a subsequent position of said pointer location.

2 more elements

A method of incrementing a pointer, the pointer designating one of a plurality of entries of a buffer, each entry comprising a first data bit associated with the entry, the data bit representative of the eligibility of the associated entry to be designated, the method comprising the steps of:

generating a plurality of local generate functions, each of said local generate functions receiving two input bits, said first input bit coupled to one of said first data bits, the second input bit coupled to one bit of a plurality of second input bits, a logic state of each one of said plurality of first input bits representative of the eligibility of a pointer to designate an entry, said plurality of second input bits representative of said pointer location at a previous time, each of said plurality of local generate functions corresponding to one of said entries of said buffer;
generating a plurality of local propagate functions, each of said plurality of local propagate functions receiving two input bits, said first input bit coupled to one of said first data bits, the second input bit coupled to one bit of said plurality of second input bits, each of said plurality of local propagate function corresponding to one of said entries of said buffer;
generating a plurality of carry bits, each one of said plurality of carry bits corresponding to one of said entries of said buffer, a first one of said plurality of carry bits being a function of an input carry bit, one of said plurality of local generate functions, and one of said plurality of local propagate functions, a second one of said plurality of carry bits being a function of another of said plurality of carry bits, another of said plurality of local generate functions, and another of said plurality of local propagate functions;
and
detecting a predetermined pattern within said plurality of carry bits, a position of said predetermined pattern identifying a subsequent position of said pointer.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/994,031Filed 21 Dec 1992
Granted: 12 Sep 1995
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 7/5055
In bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination: in which one operand is a constant, i.e.…
G06F 5/10
For changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor: having…
G06F 9/3842
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: speculative instruction execution
G06F 9/3863
Recovery, e.g. branch miss-prediction, exception handling: using multiple copies of the architectural state, e.g. shadow registers