Loadable up-down counter with asynchronous reset
AssigneeXilinx, Inc.
InventorEdward S. McGettigan
Life of this patent
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Abstract
In an FPGA having four-input lookup tables (LUTs) with parallel two-input AND gates receiving two of the four LUT input signals, associated registers, and a carry chain receiving one input signal from the AND gate output, a loadable up-down counter is formed by connecting the register output to one of the terminals serving as both a LUT input terminal and an AND gate input terminal. A load control signal is connected to another input terminal common to the LUT and the AND gate. Thus the AND gate disables the carry chain during loading of the counter and applies the count value to the carry chain during counting.
Claims7
A loadable up-down counter implemented in an FPGA comprising a plurality of stages, each stage providing one counter bit and comprising:
- a register providing a counter bit output signal G0;
- a four-input LUT programmed to generate the function
- G=(G1 AND ((G0 XOR G3)) OR (G1 AND G2)
- and receiving:
- the counter bit output signal G0,
- a load signal G1,
- an up-down signal G3, and
- a starting data value G2;
- an AND gate receiving the load signal G1 and the counter bit output signal G0 and providing an AND gate output signal;
- and
- a carry multiplexer providing a carry multiplexer output signal, and receiving as input signals the AND gate output signal and a carry multiplexer output signal from another stage.
A method of implementing a loadable up-down counter in an FPGA, comprising:
- programming a configurable logic element (CLE) to generate the function
- G=(G1 AND ((G0 XOR G3)) OR (G1 AND G2);
- providing a register to store a counter bit output signal G0;
- providing the counter bit output signal G0, a load signal G1, a starting data value G2, and an up-down signal G3 as inputs to the CLE;
- providing an AND gate having an output signal, and receiving the load signal G1 and the counter bit output signal G1 as input signals;
- and
- providing a carry multiplexer having an output signal, and receiving as input signals the AND gate output signal and a carry multiplexer output signal from another stage.
Dependencies are inferred from the claim text.