US 6,407,576 B1 · Interconnection and input/output resources for programmable logic integrated circuit devices

Abstract

A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

Claims41

Dependent claims

A programmable logic device comprising:

a plurality of regions of programmable logic, each having a plurality of input terminals and at least one output terminal, and each being programmable to selectively perform any of a plurality of logic functions on input signals applied to the input terminals to produce an output signal applied to the output terminal;
and
an interconnection network which is programmable to selectively connect the output terminal of substantially any of the regions to at least one of the input terminals of substantially any of the regions, the interconnection network including a first normal-speed portion which is programmable to selectively connect the output terminal of substantially any of the regions to at least one of the input terminals of substantially any of the regions, and a second high-speed portion which is programmable to optionally make at least part of a connection between the output terminal of substantially any of the regions and at least one of the input terminals of substantially any of the regions, wherein the high-speed portion includes a plurality of interconnection conductors, each being associated with circuitry that can programmably select any of at least a subplurality of the output terminals of the logic regions for connection to that interconnection conductor.

A programmable logic device comprising:

a plurality of regions of programmable logic, each having a plurality of input terminals and at least one output terminal, and each being programmable to selectively perform any of a plurality of logic functions on input signals applied to the input terminals to produce an output signal applied to the output terminal;
and
an interconnection network which is programmable to selectively connect the output terminal of substantially any of the regions to at least one of the input terminals of substantially any of the regions, the interconnection network including a first normal-speed portion which is programmable to selectively connect the output terminal of substantially any of the regions to at least one of the input terminals of substantially any of the regions, and a second high-speed portion which is programmable to optionally make at least part of a connection between the output terminal of substantially any of the regions and at least one of the input terminals of substantially any of the regions, wherein the regions are disposed on the device in a two-dimensional array of intersecting rows and columns of the regions, wherein the interconnection network includes a group of horizontal interconnection conductors associated with and extending along each of the rows, a group of vertical interconnection conductors associated with and extending along each of the columns, and programmable connectors configured to selectively interconnect horizontal and vertical interconnection conductors, and wherein a first subset of the conductors in each of the groups is configured to form part of the first normal-speed portion of the interconnection network, and a second subset of the conductors in each of the groups is configured to form part of the second high-speed portion of the interconnection network.

Dependencies are inferred from the claim text.

Interconnection and input/output resources for programmable logic integrated circuit devices

Life of this patent

Interconnection and input/output resources for programmable logic integrated circuit devices

Life of this patent

Abstract

Claims41