New low power adder tree structure

An adder circuit, comprising:

• a first stage configured to:
• provide a first output signal based on a first input signal received by the first stage and a second input signal received by the first stage;
• a second stage coupled to the first stage and configured to provide a second output signal by inverting the first output signal;
• a third stage coupled to the first stage and the second stage and configured to:
• provide a sum signal based on a carry-in signal received by the third stage, the first output signal, and the second output signal;
• and
• a fourth stage coupled to the first stage and the second stage and configured to:
• provide a carry-out signal based on the first input signal, the first output signal, and the second output signal.

A method of operating an adder circuit, comprising:

• receiving, by a first stage, a first input signal and a second input signal;
• and
• providing, by the first stage, a first output signal;
• inverting, by a second stage coupled to the first stage, the first output signal to provide a second output signal
• receiving, by a third stage coupled to the first stage and the second stage, a carry-in signal, the first output signal, and the second output signal
• providing, by the third stage, a sum signal;
• receiving, by a fourth stage coupled to the first stage and the second stage, the carry-in signal, the first input signal, the first output signal, and the second output signal;
• and
• providing, by the fourth stage, a carry-out signal.