G06F 30/3947
Global
Official title: global
G06F30/3947 (Global) appears on 243 US grants and 215 published applications in this corpus.
Search patents in G06F- Granted patents
- 243
- Published applications
- 215
- Assignees
- 85
- Inventors
- 529
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1996 | 1 | 0 |
| 1997 | 0 | 0 |
| 1998 | 2 | 0 |
| 1999 | 1 | 0 |
| 2000 | 1 | 0 |
| 2001 | 3 | 1 |
| 2002 | 2 | 5 |
| 2003 | 5 | 1 |
| 2004 | 5 | 5 |
| 2005 | 4 | 3 |
| 2006 | 9 | 4 |
| 2007 | 4 | 6 |
| 2008 | 6 | 8 |
| 2009 | 6 | 6 |
| 2010 | 6 | 1 |
| 2011 | 5 | 4 |
| 2012 | 3 | 4 |
| 2013 | 12 | 5 |
| 2014 | 19 | 11 |
| 2015 | 10 | 4 |
| 2016 | 2 | 3 |
| 2017 | 7 | 10 |
| 2018 | 6 | 7 |
| 2019 | 13 | 9 |
| 2020 | 18 | 17 |
| 2021 | 20 | 14 |
| 2022 | 16 | 15 |
| 2023 | 17 | 23 |
| 2024 | 14 | 12 |
| 2025 | 11 | 18 |
| 2026 | 15 | 19 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Methods and apparatus to automate a design including routing between dice6 Oct 2026US 12,755,080 B2Intel Corporation
- Method and device for designing pixel circuit, controller, and storage medium29 Sep 2026US 12,748,906 B2Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
- Runtime efficient multi-stage router flow for circuit designs21 Jul 2026US 12,688,350 B2Xilinx, Inc.
- Concurrently routing multiple partitions of an integrated circuit design23 Jun 2026US 12,664,347 B2D2S, Inc.
- Generating routes for an integrated circuit design with non-preferred direction curvilinear wiring2 Jun 2026US 12,645,858 B2D2S, Inc.
- Generating routes for an integrated circuit design with non-preferred direction wiring24 Sep 2026US 2026/0289065 A1D2S, Inc.
- Using pixel-based definition of an integrated circuit design to perform machine-trained routing17 Sep 2026US 2026/0278236 A1D2S, Inc.
- Semiconductor device manufacturing apparatus and semiconductor device manufacturing method13 Aug 2026US 2026/0236660 A1Renesas Electronics Corporation
- Method and apparatus with two-dimensional cell placement optimization13 Aug 2026US 2026/0236663 A1Samsung Electronics Co., Ltd.
- Substrate routing method6 Aug 2026US 2026/0228409 A1Advanced Semiconductor Engineering, Inc.
Most cited
By later US patents
- Tileable field-programmable gate array architecture261US 6,888,375 B2Actel Corporation · 2005
- Timing violation debugging inside place and route tool199US 7,747,975 B2LSI Corporation · 2010
- Method of placing and routing for power optimization and timing closure184US 7,992,122 B1GG Technology, Inc. · 2011
- Creating optimized physical implementations from high-level descriptions of electronic design using placement based information161US 6,145,117 ATera Systems, Inc. · 2000
- Method for designing large standard-cell base integrated circuits117US 6,567,967 B2Monterey Design Systems, Inc. · 2003