Creating optimized physical implementations from high-level descriptions of electronic design using placement based information

A computer implemented front-end design methodology for designing an electronic design, the methodology comprising:

• creating a network of logic building blocks, each logic building block representing a logic structure on a fabricated electronic design and having performance data for a plurality of different physical implementations of the logic structure, wherein the performance data is derived from placement based wire load data;
• partitioning the network of logic building blocks into a number of physical partitions;
• defining a number of block level physical implementation models of at least one partition of the number of partitions using the performance data of the logic building blocks of that partition;
• and
• creating a timing model for the electronic design by selecting optimal ones of the block level physical implementation models for all of the partitions of the electronic design thereby enabling the electronic design to be implemented in a single pass through a back-end process.

A system for implementing a front-end process for designing an electronic design the system comprising:

• a logic building block library including a number of logic building blocks, each logic building block representing a logic structure on a fabricated electronic design and having performance data for a plurality of different physical implementations of the logic structure, wherein the performance data is derived from placement based wire load data;
• a logic building block synthesis module that receives a hardware description language definition of the electronic design and creates a network of logic building blocks representing the electronic design from the library of logic building blocks;
• a partitioning module that partitions the network of logic building blocks into a number of partitions;
• and
• a chip optimization module that creates from the partitions a set of design constraints for the electronic design that enables the electronic design to be implemented to meet timing requirements associated with the electronic design in a single pass through a back-end process.

A computer implemented front-end electronic design method for automatically partitioning an electronic design:

• receiving a logic definition of the electronic design;
• synthesizing the logic definition into a network of logic structures interconnected by busses;
• using placement based wire load data to derive accurate performance characteristics for a plurality of physical implementations of each logic structure, thereby enabling the electronic design to be implemented to meet timing requirements associated with the electronic design in a single pass through a back-end process;
• tracing the busses of the network through all of the logic structures to determine which logic structures are datapath operators;
• and
• responsive to a logic structure being a datapath operator, associating the logic structure with a datapath partition.

A computer implemented method for modeling the performance of an electronic design, wherein the method has a front-end process, the method comprising:

• characterizing, during the front-end process, logic structures of the electronic design using performance data for a plurality of physical implementations of the logic structures;
• partitioning, during the front-end process, the electronic design into a number of partitions, each partition including at least one logic structure;
• creating, during the front-end process, at least one partition-level physical implementation model for at least one partition using a placement based wire load model of a routing of the logic structures of the partition and the performance data of the logic structures;
• and
• creating, during the front-end process, a design level physical implementation model using a placement based wire load model of a routing of the partitions of the electronic design, thereby enabling the electronic design to be implemented to meet timing requirements associated with the electronic design in a single pass through a back-end process.

A front-end electronic design method for optimizing an electronic design, the method comprising:

• receiving a model of the electronic design;
• synthesizing the model into at least one partition, each partition comprising a network of logic building blocks, and each logic building block having performance data derived from a corresponding placement based wire load model;
• in a partition-level optimization cycle, optimizing the at least one partition using the corresponding placement based wire load model;
• generating a set of refined design constraints based on the partition-level optimization cycle;
• in a chip-level optimization cycle, using the set of refined design constraints to optimize the electronic design using a chip-level placement based wire load model;
• generating a set of further refined design constraints based on the chip-level optimization cycle;
• and
• repeating a number of times the steps of optimizing the at least one partition, generating a set of refined design constraints, using the set of refined design constraints, and generating a set of further refined design constraints thereby enabling the electronic design to be implemented to meet timing requirements associated with the electronic design in a single pass through a back-end process.

A computer implemented front-end electronic design methodology for designing a partitioned electronic design, the methodology comprising:

• storing a library of logic building blocks having performance data for each of a plurality of different physical implementations of the logic building blocks;
• synthesizing the partitioned electronic design into a network of logic building blocks, each logic building block having performance data derived from placement based wire load data;
• and
• globally and locally optimzing the partitioned electronic design and its logic building blocks using placement based wire load data to define a set of design constraints that enables the partitioned electronic design to be implemented to meet timing requirements associated with the partitioned electronic design in a single pass through a back-end process.

A computer program product, stored on a computer readable medium, and computer program product providing a front-end methodology for designing an electronic design, wherein the computer program product is executed by a processor, causing the processor to perform the steps of:

• partitioning the electronic design into a number of partitions, at least one partition associated with at least one logic structure from a library of logic structures, wherein each logic structure has a performance envelope defined by a plurality of different physical implementations of that logic structure;
• characterizing the performance envelope of each logic structure by modeling the performance of the physical implementations associated with that logic structure using performance data derived from placement based wire load data;
• and
• globally and locally optimizing the electronic design and the partitions using placement based wire load data to define a set of design constraints that enables the electronic design to be implemented to meet timing requirements associated with the electronic design in a single pass through a back-end process.

A computer program product, stored on a computer readable medium, and computer program product providing a front-end methodology for designing an electronic design, wherein the computer program product is executed by a processor, causing the processor to perform the steps of:

• creating a network of logic building blocks, each logic building block representing a logic structure on a fabricated electronic design and having performance data that is derived from a plurality of different physical implementations of the logic structure, wherein the performance data is derived from placement based wire load data;
• partitioning the network of logic building blocks into a number of physical partitions;
• defining a number of block level physical implementation models of at least one partition of the partitions using the performance data of the logic building blocks of that partition;
• and
• creating a timing model for the electronic design by selecting optimal ones of the block level physical implementation models for all of the partitions of the electronic design thereby enabling the electronic design to be implemented in a single pass through a back-end process.

A system for implementing a front-end process for designing an electronic design, the system comprising:

• a logic building block library including a number of logic building blocks, each logic building block representing a logic structure on a fabricated electronic design and having performance data for a plurality of different physical implementations of the logic structure, wherein the performance data is derived from placement based wire load data;
• a logic building block synthesis means that receives a hardware description language definition of the electronic design and creates a network of logic building blocks representing the electronic design from the library of logic building blocks;
• a partitioning means that partitions the network of logic building blocks into a number of partitions;
• and
• a chip optimization means that creates from the partitions a set of design constraints for the electronic design that enables the electronic design to be implemented to meet timing requirements associated with the electronic design in a single pass through a back-end process.

A computer program product, stored on a computer readable medium, and computer program product providing a front-end methodology for designing an electronic design, wherein the computer program product is executed by a processor, causing the processor to perform the steps of:

• receiving a logic definition of the electronic design;
• synthesizing the logic definition into a network of logic structures inter-connected by busses;
• using placement based wire load data to derive accurate performance characteristics for a plurality of physical implementations of each logic structure, thereby enabling the electronic design to be implemented to meet timing requirements associated with the electronic design in a single pass through a back-end process;
• tracing the busses of the network through all of the logic structures to determine which logic structures are datapath operators;
• and
• responsive to a logic structure being a datapath operator, associating the logic structure with a datapath partition.